 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| DATA SHEET MOS INTEGRATED CIRCUIT PD70741 V821TM 32-/16-BIT MICROPROCESSOR The PD70741 (V821) is a 32/16-bit RISC microprocessor that uses, as its processor core, the highperformance 32-bit microprocessor PD70732 (V810TM) designed for built-in control applications. It incorporates peripheral functions such as a DRAM/ROM controller, 2-channel DMA controller, real-time pulse unit, serial interface, and interrupt controller. The V821, which offers quick real-time response, high-speed integer instructions, bit string instructions, and floating-point instructions, is ideally suited to use in OA equipment such as printers and facsimiles, image processing devices such as those used in navigation units, portable devices, and other devices demanding excellent cost performance. The functions are described in detail in the following User's Manuals, which should be read before starting design work. * V821 User's Manual Hardware : U10077E TM * V810 Family User's Manual Architecture : U10082E FEATURES The V810 32-bit microprocessor is used as the CPU core * Separate address/data bus Address bus : 24 bits Data bus : 16 bits * Built-in 1-Kbyte instruction cache memory * Pipeline structure of 1-clock pitch * Internal 4-Gbyte linear address space * 32-bit general-purpose registers: 32 Instructions ideal for various application fields * Floating-point operation instructions and bit string instructions Interrupts controller * Nonmaskable : 1 external input * Maskable : 8 external inputs and 11 types of internal sources * Priorities can be specified in units of four groups. Wait control unit * Capable of CS control over four blocks in both memory and I/O spaces. * Linear address space of each block: 16M bytes Memory access control functions * Supports DRAM high-speed page mode. * Supports page-ROM page mode. DMA controller (DMAC): 2 channels * Maximum transfer count: 65 536 * Two transfer types (fly-by (1-cycle) transfer and 2-cycle transfer) * Three transfer modes (single transfer, singlestep transfer, and block transfer) Serial interfaces : 2 channels * Asynchronous serial interface (UART): 1 channel * Synchronous serial interface (CSI): 1 channel Real-time pulse unit * 16-bit timer/event counter : 1 channel * 16-bit interval timer Watchdog timer functions Clock generator functions Standby functions (HALT, IDLE, and STOP modes) : 1 channel The information in this document is subject to change without notice. Document No. U11678EJ4V0DS00 (4th edition) Date Published June 1998 J CP(K) Printed in Japan The mark shows major revised points. (c) 1996 PD70741 ORDERING INFORMATION Part number Package 100-pin plastic LQFP (fine pitch) (14 x 14 x 1.40 mm) PD70741GC-25-8EU PIN CONFIGURATION (TOP VIEW) 100-pin plastic LQFP (fine pitch) (14 x 14 mm) PD70741GC-25-8EU Caution Connect the IC pin to GND through a resistor. 2 GND IORD IOWR NMI HLDRQ HLDAK RXD/P09/TC TXD/P08/UBE SCLK/P07 SO/P06 SI/P05 DACK1/P04 DREQ1/P03 DACK0/P02 DREQ0/P01 GND VDD TCLR/P00 BLOCK/WDTOUT INTP03 INTP02/TO01 INTP01 INTP00/TO00 INTP13/TI VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 VDD RAS UMWR LMWR/WE MRD READY CS0/REFRQ CS1 CS2 CS3 A12 A13 A14 A15 A16 GND VDD A17 A18 A19 A20 A21 A22 A23 VDD 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 GND LCAS UCAS GND X1 X2 VDD CLKOUT VDD GND A11 A10 A9 A8 A7 A6 GND VDD A5 A4 A3 A2 A1 A0 VDD 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 GND D15 D14 D13 D12 D11 D10 D9 D8 GND VDD D7 D6 D5 D4 D3 D2 D1 D0 IC RESET INTP10 INTP11 INTP12 GND PD70741 PIN NAMES A0-A23 BLOCK CLKOUT CS0-CS3 D0-D15 DACK0, DACK1 DREQ0, DREQ1 HLDAK HLDRQ INTP00-INTP03, INTP10-INTP13 IORD IOWR LCAS LMWR MRD NMI P00-P09 RAS READY REFRQ RESET RXD SCLK SI SO TC TCLR TI TO00, TO01 TXD UBE UCAS UMWR WDTOUT WE X1, X2 : Address Bus : Bus Lock : System Clock Out : Chip Select : Data Bus : DMA Acknowledge : DMA Request : Hold Acknowledge : Hold Request : Interrupt Request : I/O Read : I/O Write : Lower Column Address Strobe : Lower Memory Write : Memory Read : Non-maskable Interrupt Request : Port : Row Address Strobe : Ready : Refresh Request : Reset : Receive Data : Serial Clock : Serial Input : Serial Output : Terminal Count : Timer Clear : Timer Input : Timer Output : Transmit Data : Upper Byte Enable : Upper Column Address Strobe : Upper Memory Write : Watchdog Timer Output : Write Enable : Crystal Oscillator 3 PD70741 INTERNAL BLOCK DIAGRAM CLKOUT TI V821 X1 X2 RESET CG CPU (V810) ICU RPU 4 TO00,TO01 TCLR INTP00-INTP03, INTP10-INTP13 TXD RXD SCLK SI SO PORT00-PORT09 UART WDTOUT WDT CSI HLDAK HLDRQ DREQ0, DREQ1 DACK0, DACK1 TC BAU PORT DMAC DRAMC BIU ROMC WCU/CS NMI A0-A23 D0-D15 UBE RAS LCAS UCAS REFRQ WE MRD IORD IOWR LMWR UMWR READY CS0-CS3 4 PD70741 CONTENTS 1. PIN FUNCTIONS ........................................................................................................................ 1.1 1.2 1.3 Port Pins ......................................................................................................................................... Non-Port Pins ................................................................................................................................. Pin I/O Circuits and Processing of Unused Pins ...................................................................... 8 8 8 10 2. INTERNAL UNITS ...................................................................................................................... 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 Bus Interface Unit (BIU) ................................................................................................................ Wait Control Unit (WCU) ............................................................................................................... DRAM Controller (DRAMC) ........................................................................................................... ROM Controller (ROMC) ................................................................................................................ Interrupt Controller ........................................................................................................................ DMA Controller (DMAC) ................................................................................................................ Serial Interfaces (UART/CSI) ........................................................................................................ Real-Time Pulse Unit (RPU) ......................................................................................................... Watchdog Timer (WDT) ................................................................................................................. Clock Generator (CG) .................................................................................................................... Bus Arbitration Unit (BAU) ........................................................................................................... Port .................................................................................................................................................. 12 12 12 12 12 12 12 12 12 13 13 13 13 3. CPU FUNCTIONS ....................................................................................................................... 3.1 3.2 Features .......................................................................................................................................... Address Space ............................................................................................................................... 3.2.1 3.2.2 3.3 3.3.1 3.3.2 3.4 3.5 Memory map ................................................................................................................... I/O map ............................................................................................................................ Program register set ..................................................................................................... System register set ........................................................................................................ 14 14 14 15 16 17 18 19 20 23 23 25 26 CPU Register Set ........................................................................................................................... Built-in Peripheral I/O Registers .................................................................................................. Data Types ...................................................................................................................................... 3.5.1 3.5.2 Data types ....................................................................................................................... Data alignment ............................................................................................................... 3.6 Cache ............................................................................................................................................... 4. INTERRUPT/EXCEPTION HANDLING FUNCTIONS ............................................................... 4.1 Features .......................................................................................................................................... 27 27 5. WAIT CONTROL FUNCTIONS .................................................................................................. 5.1 Features .......................................................................................................................................... 30 30 5 PD70741 6. MEMORY ACCESS CONTROL FUNCTIONS .......................................................................... 6.1 DRAM Controller (DRAMC) ........................................................................................................... 6.1.1 6.1.2 6.1.3 6.1.4 6.2 6.2.1 Features .......................................................................................................................... Address multiplexing function .................................................................................... Refresh function ............................................................................................................ Self-refresh function ...................................................................................................... on-page/off-page decision ............................................................................................ 32 32 32 32 33 33 33 33 ROM Controller (ROMC) ................................................................................................................ 7. DMA FUNCTIONS (DMA CONTROLLER) ............................................................................... 7.1 Features .......................................................................................................................................... 35 35 8. SERIAL INTERFACE FUNCTION ............................................................................................. 8.1 8.2 8.3 8.4 Features .......................................................................................................................................... Asynchronous Serial Interface (UART) ...................................................................................... 8.2.1 8.3.1 8.4.1 Features .......................................................................................................................... Features .......................................................................................................................... Configuration and function .......................................................................................... Synchronous Serial Interface (CSI) ............................................................................................. Baud Rate Generator (BRG) ......................................................................................................... 37 37 37 37 39 39 40 40 9. TIMER/COUNTER FUNCTIONS (REAL-TIME PULSE UNIT) ................................................. 9.1 Features .......................................................................................................................................... 41 41 10. WATCHDOG TIMER FUNCTIONS ............................................................................................ 10.1 10.2 Features .......................................................................................................................................... Operation ........................................................................................................................................ 43 43 44 11. PORT FUNCTIONS .................................................................................................................... 11.1 Features .......................................................................................................................................... 45 45 12. CLOCK GENERATION FUNCTIONS ........................................................................................ 12.1 Features .......................................................................................................................................... 46 46 13. STANDBY FUNCTIONS ............................................................................................................. 13.1 13.2 Features .......................................................................................................................................... Standby Mode ................................................................................................................................ 47 47 47 14. RESET FUNCTIONS .................................................................................................................. 14.1 14.2 Features .......................................................................................................................................... Pin Functions ................................................................................................................................. 49 49 49 15. INSTRUCTION SET .................................................................................................................... 15.1 15.2 Instruction Format ......................................................................................................................... Instruction Mnemonic (In Alphabetical Order) .......................................................................... 50 50 52 6 PD70741 16. ELECTRICAL SPECIFICATIONS .............................................................................................. 62 17. PACKAGE DRAWINGS ............................................................................................................. 107 18. RECOMMENDED SOLDERING CONDITIONS ........................................................................ 108 7 PD70741 1. PIN FUNCTIONS 1.1 Port Pins Pin name P00 P01 P02 P03 P04 P05 P06 P07 P08 P09 Input/output Input/output Port 0 10-bit input/output port Can be set for input/output bit. Function Dual-function pin TCLR DREQ0 DACK0 DREQ1 DACK1 SI SO SCLK TXD/UBE RXD/TC Remark After a reset is released, each port pin is set as an input port pin. 1.2 Non-Port Pins (1/2) Pin name A0-A23 D0-D15 READY HLDRQ HLDAK BLOCK MRD LMWR UMWR IORD IOWR UBE RESET X1, X2 Input/output Tristate output Tristate input/output Input Input Output Output Tristate output Tristate output Tristate output Tristate output Tristate output Tristate output Input Input Address bus signal Bidirectional data bus signal Bus cycle termination permit signal Bus mastership request signal Bus mastership permit signal Bus mastership prohibit signal Read strobe signal to memory Write strobe signal to lower data in memory Write strobe signal to upper data in memory Read strobe signal to I/O data Write strobe signal to I/O data Data bus upper data enable signal System reset input Crystal connection/external clock input WE TXD/P08 Function Dual-function pin WDTOUT - 8 PD70741 (2/2) Pin name CLKOUT CS0 CS1 CS2 CS3 INTP00 INTP01 INTP02 INTP03 INTP10 INTP11 INTP12 INTP13 NMI REFRQ RAS LCAS UCAS WE DREQ0 DREQ1 DACK0 DACK1 TC TO00 TO01 TCLR TI TXD RXD SCLK SO SI WDTOUT IC VDD GND Input Input Output Input Input/output Output Input Output External clear or start signal input to timer 0 External count clock input to timer 0 UART serial data output UART serial data input CSI serial clock input/output CSI serial data output CSI serial data input WDT overflow signal Internal connection (must be connected to GND through a resistor) Supplies positive power. Ground potential Input Tristate output Tristate output Tristate output Tristate output Tristate output Input Input Output Output Output Output Nonmaskable interrupt request input Refresh request signal to DRAM Row address strobe signal to DRAM Column address strobe signal to lower data in DRAM Column address strobe signal to upper data in DRAM Write strobe signal to DRAM DMA request signal (channel 0) DMA request signal (channel 1) DMA permit signal (channel 0) DMA permit signal (channel 1) DMA end signal RPU pulse output LMWR P01 P03 P02 P04 RXD/P09 INTP00 INTP02 P00 INTP13 UBE/P08 TC/P09 P07 P06 P05 BLOCK CS0 TI TO01 Input Interrupt request input TO00 Input/output Output Tristate output System clock output Chip select signal REFRQ Function Dual-function pin - 9 PD70741 1.3 Pin I/O Circuits and Processing of Unused Pins Table 1-1 shows the I/O circuit type of each pin and the processing for unused pins. Figure 1-1 shows the I/O circuit of each type. Table 1-1. I/O Circuits Type of Each Pin and Recommended Connection of Unused Pins Pin P00/TCLR P01/DREQ0 P02/DACK0 P03/DREQ1 P04/DACK1 P05/SI P06/SO P07/SCLK P08/TXD/UBE P09/RXD/TC D0-D15 A0-A7, A16-A18 A8-A15, A19-A23 READY HLDRQ HLDAK BLOCK/WDTOUT MRD LMWR/WE UMWR IORD IOWR CLKOUT CS0/REFRQ CS1-CS3 INTP00/TO00 INTP01 INTP02/TO01 INTP03 INTP10-INTP12 INTP13/TI NMI RESET RAS LCAS UCAS X2 IC Connected to GND through a resistor. 4 Open 8 2 8 2 Connected to VDD through a resistor. Connected to VDD through a resistor. Connected to VDD through a resistor. Connected to VDD through a resistor. 4 4 1 Open Connected to GND through a resistor. Connected to VDD through a resistor. Open 5 Open 5 I/O circuit type Input status: Recommended connection Individually connected to VDD or GND through a resistor. Output status: Open 10 PD70741 Figure 1-1. Pin I/O Circuits Type 1 VDD Type 5 VDD Data P-ch IN N-ch Output disable N-ch P-ch IN/OUT Input enable Type 2 Type 8 VDD Data IN P-ch IN/OUT Output disable N-ch Schmitt trigger input with hysteresis characteristics Type 4 VDD Data P-ch OUT Output disable N-ch Push-pull output which can output high impedance (Both the positive and negative channels are off.) 11 PD70741 2. INTERNAL UNITS 2.1 Bus Interface Unit (BIU) Controls the pins of the address bus, data bus, and control bus. A bus cycle activated by the CPU or DMAC is controlled via the WCU, DRAMC, and ROMC. 2.2 Wait Control Unit (WCU) Manages the four blocks corresponding to four chip select signals (CS0-CS3). This block generates chip select signals, performs wait control, and selects a bus cycle type. 2.3 DRAM Controller (DRAMC) Generates the RAS, UCAS, and LCAS signals (2CAS control) and controls access to DRAM. This block supports DRAM high-speed page mode. Access to DRAM can be of either of two types, each having a different cycle, normal access (off-page) or high-speed page access (on-page). 2.4 ROM Controller (ROMC) Supports access to ROM supporting a page access function. Performs address comparison relative to the previous bus cycle and performs wait control for normal access (offpage)/page access (on-page). It supports page widths of 8-64 bytes. 2.5 Interrupt Controller Handles maskable interrupt requests (INTP00-INTP03, INTP10-INTP13) from both the built-in and external peripheral hardware. Priorities can be specified for these interrupt requests, in units of four groups. It can apply multiple handling control to the interrupt sources. 2.6 DMA Controller (DMAC) Transfers data between memory and I/O, as instructed by the CPU. There are two address modes, fly-by (1-cycle) transfer and 2-cycle transfer. There are three bus modes, single transfer, single-step transfer, and block transfer. 2.7 Serial Interfaces (UART/CSI) As serial interfaces, the V821 features an asynchronous serial interface (UART) and a synchronous serial interface (CSI), one channel being assigned to each. The UART transfers data via pins TXD and RXD. The CSI transfers data via pins SO, SI, and SCLK. Either the baud rate generator or the system clock can be selected as the serial clock source. 2.8 Real-Time Pulse Unit (RPU) This block incorporates a 16-bit timer/event counter and a 16-bit interval timer. It can calculate pulse intervals and frequencies and output programmable pulses. 12 PD70741 2.9 Watchdog Timer (WDT) This block incorporates an 8-bit watchdog timer to detect a program hanging up or system errors. If the watchdog timer overflows, the WDTOUT pin becomes active. 2.10 Clock Generator (CG) Supplies clock pulses at a frequency five times greater than that of the oscillator connected to pins X1 and X2 (when the built-in PLL is being used) or at half the frequency (when the built-in PLL is not being used) of the operating clock pulses for the CPU. Also, instead of connecting an oscillator, external clock pulses can be input. 2.11 Bus Arbitration Unit (BAU) Arbitrates any contention over bus mastership between the bus masters (CPU, DRAMC, DMAC, external bus master). Bus mastership can be switched in each bus cycle and also in the idle state. 2.12 Port Port 0 provides a total of ten input/output port pins. The pins can be used as either port or control pins. 13 PD70741 3. CPU FUNCTIONS The CPU has functions equivalent to those of the V810 microprocessor, designed for built-in control. It offers bit string instructions, floating-point instructions, and quick real-time response. 3.1 Features The features of the CPU are: * High-performance 32-bit RISC microprocessor * Built-in 1-Kbyte cache memory * Pipeline structure of 1-clock pitch * 16-bit data bus * 32-bit general-purpose registers: 32 * 4-Gbyte linear address space * Instructions ideal for various application fields * Floating-point operation instructions (conforming to the IEEE754 data format) * Bit string instructions * High-speed interrupt response * Debug support functions 3.2 Address Space The V821 supports internal memory and I/O spaces of 4G bytes each. The V821 outputs 24-bit addresses to memory and I/O, such that the addresses range from 0 to 224 - 1. In byte data, bit 0 is defined as the LSB (Least Significant Bit) and bit 7 as the MSB (Most Significant Bit). In multiplebyte data, bit 0 of the byte data in the lower address is defined as the LSB and bit 7 of the byte data in the upper address as the MSB, unless noted otherwise. In the case of the V821, 2-byte data is referred to as halfword data, and 4-byte data as word data. In this data sheet, in representations of multiple-byte memory and I/O data, the right address corresponds to the lower address and the left address to the upper address, as shown below. Byte of address A 7 0 A (address) 15 87 0 Halfword of address A A+1 31 24 23 16 15 A (address) 87 0 Word of address A/short real A+3 A+2 A+1 A (address) 14 PD70741 3.2.1 Memory map Figure 3-1 shows the memory map of the V821. The internal 4-Gbyte memory space is divided into blocks of 1G byte each. Each block has a linear address space of 16M bytes. (The lower 24 bits of a 32-bit address are output.) Figure 3-1. Memory Map FFFFFFFFH Interrupt handler tableNote FFFFFE00H FFFFFDFFH Block 3 C0000000H BFFFFFFFH Block 2 80000000H 7FFFFFFFH Block 1 40000000H 3FFFFFFFH Block 0 00000000H Note See Table 4-1 for details. 15 PD70741 3.2.2 I/O map Figure 3-2 shows the I/O map of the V821. The internal 4-Gbyte memory space is divided into blocks of 1G byte each. Each block has a linear address space of 16M bytes. (The lower 24 bits of a 32-bit address are output.) The V821 reserves I/O addresses C0000000H-FFFFFFFFH (I/O block 3) as an internal I/O space. Each unit is mapped to this internal I/O space. See Section 3.4 for details of the configuration of the internal I/O space. Figure 3-2. I/O Map FFFFFFFFH Block 3 (Internal I/O) C0000000H BFFFFFFFH Block 2 80000000H 7FFFFFFFH Block 1 40000000H 3FFFFFFFH Block 0 00000000H 16 PD70741 3.3 CPU Register Set The registers of the V821 belong to one of two sets, the general-purpose program register set and the dedicated system register set. All registers are 32 bits in wide. Program register set 31 r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 r31 31 PC String Destination Bit Offset String Source Bit Offset String Length String Destination String Source Link Pointer (lp) 0 Program Counter 31 ADTRE Zero Register Reserved for Address Generation Handler Stack Pointer (hp) Stack Pointer (sp) Global Pointer (gp) Text Pointer (tp) 0 31 EIPC EIPSW 31 FEPC FEPSW 31 ECR 31 PSW 31 PIR 31 TKCW 31 CHCW System register set 0 Exception/Interrupt PC Exception/Interrupt PSW 0 Fatal Error PC Fatal Error PSW 0 Exception Cause Register 0 Program Status Word 0 Processor ID Register 0 Task Control Word 0 Cache Control Word 0 Address Trap Register 17 PD70741 3.3.1 Program register set The program register set includes general-purpose registers and a program counter. (1) General-purpose registers The V821 has 32 general-purpose registers, r0-r31. These registers can be used for data or address variables. Registers r0 and r26-r30 are used implicitly with instructions. Caution is therefore necessary when using these registers. Registers r1-r5 and r31 are used implicitly by the assembler and the C compiler. Before using these registers, therefore, the contents of the registers must be saved to prevent their being destroyed. After using the registers, their contents must be restored. Table 3-1. Program Registers Name r0 r1 r2 r3 r4 r5 r6-r25 r26 r27 r28 r29 r30 r31 Zero register Assembler-reserved register Handler stack pointer Stack pointer Global pointer Text pointer String destination start bit offset String source start bit offset String length register String destination start address register String start address register Link pointer Stores a return point address according to the execution of a JAL instruction. Use Always stores zeros. Used as a working register to create 32-bit immediate. Used as a stack pointer for the handler. Used to create a stack frame at a function call. Used to access a global variable in a data area. Points to the top of a text area Register for an address/data variable Used to execute a bit string instruction. Explanation (2) Program counter Stores the address of an instruction while a program is running. Bit 0 of the program counter (PC) is fixed to 0, thus preventing a branch to an odd address. It is initialized to FFFFFFF0H at reset. 18 PD70741 3.3.2 System register set System registers are used to control the state of the CPU and store interrupt information. Table 3-2. System Register Numbers No. 0 Register name EIPC Use Registers for saving the current status upon the occurrence of an exception or interrupt Explanation Retain the contents of PC and PSW if an exception or interrupt occurs. Note, however, that there is only one pair of these registers. When multiple interrupts are allowed, therefore, the contents of the registers must be saved by the program. Retain the contents of PC and PSW if an NMI or double exception occurs. 1 EIPSW 2 3 4 FEPC FEPSW ECR Registers for saving the current status upon the occurrence of an NMI or double exception Exception source register Stores the source of an exception, maskable interrupt, or NMI. The upper 16 bits of this register are called "FECC" and set to the exception code of an NMI/double exception. The lower 16 bits are called "EICC" and set to the exception code of an exception/interrupt. The program status word is a set of flags indicating the state of the program (result of executing an instruction) and the state of the CPU. Used to identify a CPU type number. Used to control a floating-point operation. 5 PSW Program status word 6 7 8-23 24 25 PIR TKCW Reserved CHCW ADTRE Processor ID register Task control word Cache control word Address trap register Used to control the built-in instruction cache. Stores the address used to detect an address match with PC, and to generate an address trap. 26-31 Reserved Read and write operations made to these system registers can be performed using the system register load/store instructions (LDSR and STSR) with the system register numbers specified. 19 PD70741 3.4 Built-in Peripheral I/O Registers The built-in peripheral I/O registers are allocated to the 256-byte area between C0000000H and C00000FFH in the 1-Gbyte space between C0000000H and FFFFFFFFH. Starting from address C0000100H, 256-byte images are created every 256 bytes. The least significant bit of an address is not decoded. Thus, when byte access is attempted to a register at an odd address (2n+1), a register at an even address (2n) is actually performed. When 16-bit access is attempted to an 8-bit I/O register, the upper eight bits are ignored for write, and become undefined for read. Table 3-3 lists the built-in peripheral I/O registers. 20 PD70741 Table 3-3. Built-in Peripheral I/O Registers (1/2) Manipulatable bits 8-bits C0000010 C0000012 C0000014 C0000020 C0000022 C0000024 C0000026 C0000028 C000002A C000002C C0000040 C0000042 C0000044 C0000046 C0000048 C000004A C000004C C000004E C0000050 C0000052 C0000054 C0000056 C0000060 C0000062 C0000064 C0000066 C0000068 C0000070 C0000072 C0000074 C0000076 C0000078 C000007C C000007E C0000080 C0000082 Port mode control register 0 Port mode register 0 Port register 0 Bus cycle type control register Programmable wait control register 0 Programmable wait control register 1 Programmable wait control register 2 DRAM configuration register Refresh control register Page-ROM configuration register DMA source address register 0H DMA source address register 0L DMA destination address register 0H DMA destination address register 0L DMA source address register 1H DMA source address register 1L DMA destination address register 1H DMA destination address register 1L DMA byte count register 0 DMA byte count register 1 DMA channel control register 0 DMA channel control register 1 Timer unit mode register 0 Timer control register 0 Timer control register 1 Timer output control register 0 Timer overflow status register Timer register 0 Capture/compare register 00 Capture/compare register 01 Capture/compare register 02 Capture/compare register 03 Timer register 1 Compare register 1 PMC0 PM0 P0 BCTC PWC0 PWC1 PWC2 DRC RFC PRC DSA0H DSA0L DDA0H DDA0L DSA1H DSA1L DDA1H DDA1L DBC0 DBC1 DCHC0 DCHC1 TUM0 TMC0 TMC1 TOC0 TOVS TM0 CC00 CC01 CC02 CC03 TM1 CM1 o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o o 16-bits o o o 0000H 03FFH Not defined 01H 77H 77H 77H 81H 80H 80H Not defined Not defined Not defined Not defined Not defined Not defined Not defined Not defined Not defined Not defined 0000H 0000H 0A00H 00H 00H 03H 00H 0000H Not defined Not defined Not defined Not defined 0000H Not defined 00H 00H Address Function register name Abbreviation Initial value Asynchronous serial interface mode register ASIM Asynchronous serial interface status register ASIS 21 PD70741 Table 3-3. Built-in Peripheral I/O Registers (2/2) Manipulatable bits 8-bits C0000084 C0000086 C0000088 C000008A C0000090 C0000092 C00000A0 C00000A2 C00000B0 C00000B2 C00000B4 C00000B6 C00000B8 C00000C0 C00000D0 C00000E0 Reception buffer Reception buffer L Transmission shift register Transmission shift register L Synchronous serial interface mode register Serial I/O shift register Baud rate generator register RXB RXBL TXS TXSL CSIM SIO BRG o o o o o o o o o o o o o o o 16-bits o Not defined Not defined Not defined Not defined 00H Not defined Not defined 00H E4H 0000H 0000H FFFFH AAAAH 00H 00H 03H Address Function register name Abbreviation Initial value Baud rate generator prescale mode register BPRM Interrupt group priority register Interrupt clear register Interrupt request register Interrupt request mask register ICU mode register WDT mode register Standby control register Clock control register IGP ICR IRR IMR IMOD WDTM STBC CGC 22 PD70741 3.5 Data Types 3.5.1 Data types The data types supported by the V821 are as follows: * Integer (8, 16, 32 bits) * Unsigned integer (8, 16, 32 bits) * Bit string * Single-precision floating-point data (32 bits) (1) Data type and addressing The V821 uses the little-endian data addressing. In this addressing, if fixed-length data is located in a memory area, the data must be either of the data types shown below. (a) Byte A byte is consecutive 8-bit data whose first-bit address is aligned to a byte boundary. Each bit in a byte is numbered from 0 to 7: LSB (the least significant bit) is bit 0 and MSB (the most significant bit) is bit 7. To access a byte, specify address A. (See diagram below.) 7 0 A (b) Halfword A halfword is consecutive 16-bit (= 2 bytes) data whose first-bit address is aligned to a halfword boundary. Each bit in a halfword is numbered from 0 to 15: LSB (the least significant bit) is bit 0 and MSB (the most significant bit) is bit 15. To access a halfword, specify the address A only (lowest bit must be 0). 15 87 0 A+1 A (c) Word/short real A word, also called short real, is consecutive 32-bit (= 4 bytes) data whose first-bit address is aligned to a word boundary. Each bit in a word is numbered from 0 to 31: LSB (the least significant bit) is bit 0 and MSB (the most significant bit) is bit 31. To access a word or short real, specify the address A only (lower two bits must be 0). 31 24 23 16 15 87 0 A+3 A+2 A+1 A 23 PD70741 (2) Integer In the V821, all integers are expressed in the two's-complement binary notation, and are composed of either 8 bits, 16 bits, or 32 bits. Regardless of the data length, bit 0 is the least significant bit, and higher-numbered bits express higher digits of the integer with the highest bit expressing its sign. Data length Byte Halfword Word 8 bits 16 bits 32 bits Range -128 to +127 -32 768 to +32 767 -2 147 483 648 to +2 147 483 647 (3) Unsigned integer An unsigned integer is either zero or a positive integer unlike the integer explained in (2) which can be negative as well as zero and positive. Unsigned integers are expressed in the binary notation in the same way as integers, and are either 8 bits, 16 bits, or 32 bits long. Regardless of the data length, the bit assignments are the same as in the case of integers except that unsigned integers do not include a sign bit; the highest bit is also a part of the integer. Data length Byte Halfword Word 8 bits 16 bits 32 bits Range 0 to 255 0 to 65 535 0 to 4 294 967 295 (4) Bit string A bit string is a type of data whose bit length is variable from 0 to 232 - 1. To specify a bit-string data, define the following three attributes. * A : address of the string data's first word (lower two bits must be 0.) * B : in-word bit offset in the string data (0 to 31) * M : bit length of the string data (0 to 232 - 1) The above three attributes may vary depending on the bit-string data manipulation direction: upward or downward, as shown below. The former is the direction from lower addresses to higher addresses while the latter is the direction from higher to lower addresses. 24 PD70741 M-1 M 0 A+8 D A+4 A (Word boundary) B Attribute First-word address (0s in bits 1 and 0) In-word bit offset (0 to 31) Bit length (0 to 232 - 1) Upward A B M Downward A+4 D M (5) Single-precision floating-point data This data type is 32 bits long and its bit allocation complies with the IEEE single format. A single-precision floatingpoint data consists of 1-bit mantissa sign bit, 8-bit exponent, and 23-bit mantissa. The exponent is offsetexpressed from the bias value - 127, and the mantissa is binary-expressed with the integer part omitted. 31 30 s exp (8) 23 22 mantissa (23) 0 3.5.2 Data alignment In the V821, a word data must be aligned to a word boundary (with the lowest two bits of the address fixed to 0s), and a halfword data to a halfword boundary (with the lowest bit of the address fixed to 0). If a data is not aligned as specified, the lowest two bits (in the case of word) or one bit (in the case of halfword) of its address will forcibly be masked with 0s when the data is accessed. 25 PD70741 3.6 Cache Figure 3-3 shows the instruction cache configuration provided to the V821. Figure 3-3. Cache Configuration : 1 Kbytes Mapping system : direct map : 8 bytes Block size Sub-block size : 4 bytes Capacity 31 Memory address TAG 10 9 Index 32 Offset 0 Tag memory (ICHT27 to ICHT0) Data memory (ICHD31 to ICHD0) 27 Entry 0 Entry 1 22 21 TAG31 to TAG10 0 31 Sub-block (4 bytes) 0 Block (8 bytes) 128 entries 128 blocks Entry 127 Valid bits (1 bit for every 4 bytes) NECRV (Reserved by NEC) 26 PD70741 4. INTERRUPT/EXCEPTION HANDLING FUNCTIONS The V821 features an interrupt controller (ICU) that is dedicated to interrupt handling. The V821 thus supports a powerful interrupt handling function capable of handling interrupt requests issued by up to 16 sources. As referred to in this manual, an interrupt is an event which occurs independently of program execution while an exception is an event that depends on program execution. In general, an exception assumes a higher priority than an interrupt. The V821 can handle interrupt requests issued by both built-in peripheral hardware and external devices. Exception handling can be triggered by executing an instruction (TRAP instruction) as well as by the occurrence of an exception (such as an address trap or invalid instruction code). 4.1 Features Interrupts * Nonmaskable interrupt : 1 source * Maskable interrupt : 15 sources * Programmable priority control with four groups * Multiple interrupt handling control according to priority * Mask specification for each maskable interrupt request * Valid edge specification for external interrupt requests * The noise eliminator introducing an analog delay (60 to 300 ns) is incorporated into the nonmaskable interrupt (NMI) pin. Exceptions * Software exception : 32 sources * Exception trap : 10 sources Table 4-1 lists the interrupt and exception sources. 27 PD70741 Table 4-1. Interrupts (1/2) Type Category Group Priority in group Reset Interrupt Name RESET NMI Interrupt/exception source Source Reset input NMI input Unit Exception code FFF0H FFD0H Handler address FFFFFFF0H FFFFFFD0H Return PCNote 1 Undefined Next PCNote 2 Next PC Next PC Current PC NonInterrupt maskable Software exception Exception Exception trap Exception - - TRAP1nH TRAP0nH DP-EX AD-TR I-OPC trap instruction trap instruction Double exception Address trap Invalid instruction code Division by zero Invalid floatingpoint operation Floating-point division by zero Floating-point overflow Floating-point underflowNote 4 Floating-point degraded precisionNote 4 Floating-point reserved operand - FFBnH FFAnH Note 3 FFFFFFB0H FFFFFFA0H FFFFFFD0H FFFFFFC0H FFFFFF90H FFC0H FF90H - - DIV0 FIZ - FF80H FF70H FFFFFF80H FFFFFF60H - - FZD - FF68H FFFFFF60H - - FOV - FF64H FFFFFF60H - - FUD - FF62H FFFFFF60H - - FPR - FF61H FFFFFF60H - - FRO - FF60H FFFFFF60H Remark n = 0H to FH Notes 1. PC value saved in EIPC or FEPC at the beginning of interrupt/exception handling 2. Return PC = current PC if an interrupt occurred during the execution of an instruction which was stopped by an interrupt (DIV/DIVU, floating-point, and bit string instructions). 3. The exception code for the exception which occurred first is written into in the 16 low-order bits of ECR, while and that for the second exception is written into the 16 high-order bits. 4. The V821 is not subject to floating-point underflow or degraded precision exceptions. 28 PD70741 Table 4-1. Interrupts (2/2) Type Category Group Priority in group Maskable Interrupt GR3 3 2 Name RESERVED INTOV0 Interrupt/exception source Source Reserved Timer 0 overflow UART reception error INTP13 pin input UART reception end UART transmission end CSI transmission/reception end INTP12 pin input DMA transfer end INTP00 pin input/CC00 match INTP01 pin input/CC01 match INTP11 pin input CM1 match INTP02 pin input/CC02 match INTP03 pin input/CC03 match INTP10 pin input Unit RPU Exception code FEF0H FEE0H Handler address FFFFFEF0H FFFFFEE0H Return PCNote 1 Next PCNote 2 1 INTSER UART FED0H FFFFFED0H 0 INTP13 External FEC0H FFFFFEC0H GR2 3 INTSR UART FEB0H FFFFFEB0H 2 INTST UART FEA0H FFFFFEA0H 1 INTCSI CSI FE90H FFFFFE90H 0 INTP12 External FE80H FFFFFE80H GR1 3 INTDMA DMAC FE70H FFFFFE70H 2 INTP00/ INTCC00 External/ RPU FE60H FFFFFE60H 1 INTP01/ INTCC01 External/ RPU FE50H FFFFFE50H 0 INTP11 External FE40H FFFFFE40H GR0 3 2 INTCM1 INTP02/ INTCC02 RPU External/ RPU FE30H FE20H FFFFFE30H FFFFFE20H 1 INTP03/ INTCC03 External/ RPU FE10H FFFFFE10H 0 INTP10 External FE00H FFFFFE00H Notes 1. PC value saved in EIPC or FEPC at the beginning of interrupt/exception handling 2. Return PC = current PC if an interrupt occurred during the execution of an instruction which was stopped by an interrupt (DIV/DIVU, floating-point, and bit string instructions). Caution The exception code and handler address for a maskable interrupt assume the values existing when the default priority is specified. 29 PD70741 5. WAIT CONTROL FUNCTIONS The wait control unit (WCU) manages the four blocks corresponding to the four chip select signals, generates the chip select signals, performs wait control, and selects the bus cycle types. 5.1 Features * Able to control up to four blocks in the memory and I/O spaces * Linear address space of each block: 16 Mbytes * Wait control * Automatic insertion of 0-7 waits per block * Insertion of waits using the READY pin * Bus cycle selection function * Page-ROM cycle selectable (address block 3) * DRAM cycle selectable (address block 0) Figure 5-1. Memory and I/O Maps (1) Memory map (2) I/O map FFFFFFFFH Block 3 (1 Gbyte) C0000000H BFFFFFFFH Block 2 (1 Gbyte) 80000000H 7FFFFFFFH Block 1 (1 Gbyte) 40000000H 3FFFFFFFH Block 0 (1 Gbyte) 00000000H 16 Mbytes Image Image FFFFFFFFH Block 3 (1 Gbyte) Internal I/O Block 2 (1 Gbyte) C0000000H BFFFFFFFH Image 16 Mbytes Image Image 80000000H 7FFFFFFFH Block 1 (1 Gbyte) 40000000H 3FFFFFFFH Block 0 (1 Gbyte) 16 Mbytes Image Image Image 00000000H Image 30 PD70741 Table 5-1. Bus Cycles during Which the Wait Function Is Effective Bus cycle SRAM (ROM) cycle (Blocks 0-3) DRAM cycle (Block 0) off-page on-page Page-ROM cycle (Block 3) off-page on-page External I/O cycle (Blocks 0-2) Internal I/O cycle (Block 3) CBR refresh cycle CBR self-refresh cycle Fly-by DMA transfer SRAM (ROM) cycle (Blocks 0-3) DRAM cycle (Block 0) off-page on-page Page-ROM cycle (Block 3) off-page on-page Halt acknowledge cycle Machine fault cycle (I/O block 0 write) 0-7 waits 2-7 waits 0-7 waits 0-7 waits 0-7 waits Fixed (0 wait) 0-7 wait o o x x x x o Programmable wait 0-7 waits 2 or 3 waits 0 or 1 wait 0-7 waits 0 or 1 wait 0-7 waits 1 or 2 waits Fixed (3 waits) o o x x x o x o x Wait with the READY pin Remark o: Effective x: Not effective 31 PD70741 6. MEMORY ACCESS CONTROL FUNCTIONS 6.1 DRAM Controller (DRAMC) The DRAM controller (DRAMC) generates the REFRQ, RAS, LCAS, and UCAS signals, and controls access to DRAM. Access to DRAM is achieved by multiplexing the DRAM row and column addresses and outputting them from the address pins. The microprocessor assumes the connected DRAM to be of x 4 bits or more, and that it supports high-speed page mode. There are two types of DRAM access cycles, on-page (2 or 3 clock pulses) and off-page (4 or 5 pulses). Refresh uses the CAS before RAS method, allowing the user to set any refresh period. In IDLE and STOP modes, CBR self-refresh is performed. 6.1.1 Features * * * * Generates the REFRQ, RAS, LCAS, and UCAS signals. Supports DRAM high-speed page mode. Address multiplexing function: 8, 9, 10, and 11 bits CBR refresh and CBR self-refresh functions 6.1.2 Address multiplexing function In the DRAM cycle, row and column addresses are multiplexed according to the value of the DAW bits of the DRAM configuration register (DRC), then output, as shown in Figure 6-1. In Figure 6-1, a0-a23 are the addresses output from the CPU, while A0-A23 are the address pins of the V821. For example, if DAW = 11, row address a12-a22 and column address a1-a11 are output from address pins (A1-A11). Table 6-1 lists the relationship between the connectable DRAMs and address multiplexing widths. Depending on the connected DRAM, the DRAM space can be between 128 Kbytes and 8 Mbytes. Figure 6-1. Output of Row and Column Addresses Address pin Row address DAW = 11 DAW = 10 DAW = 01 A23 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 a23 a23 a23 a23 a23 a16 a16 a16 a16 a15 a14 a13 a23 a22 a21 a20 a15 a14 a23 a22 a21 a20 a19 a15 a23 a22 a21 a20 a19 a18 a23 a22 a21 a20 a19 a18 a17 a19 a18 a17 a16 a15 a14 a13 a12 a11 a18 a17 a16 a15 a14 a13 a12 a11 a10 a17 a16 a15 a14 a13 a12 a11 a10 a16 a15 a14 a13 a12 a11 a10 a9 a9 a8 a0 DAW = 00 Column address 32 PD70741 Table 6-1. Examples of DRAM and Address Multiplexing Width Address multiplexing width DRAM capacity (in bits) and configuration 256 K 8 bits 9 bits 64 K x 4 10 bits 11 bits 1M 256 K x 4 4M 256 K x 16 512 K x 8 1Mx4 16 M 1 M x 16 2Mx8 4Mx4 128 K 512 K 1M 2M 4M 8M DRAM space (in bytes) 6.1.3 Refresh function DRAMC can automatically generate the distributed CBR refresh cycle needed to refresh external DRAM. Whether refresh should be enabled or disabled, and the refresh interval, are specified using the refresh control register (RFC). While another bus master is occupying a bus, DRAMC cannot forcibly acquire the bus. In this case, in response to a refresh request issued from DRAMC, BAU makes the HLDAK pin inactive to post notification of the occurrence of a refresh request. In this state, by making the HLDRQ pin inactive, the refresh cycle is activated. 6.1.4 Self-refresh function DRAMC generates the CBR self-refresh cycle in IDLE and STOP modes. The self-refresh cycle is activated by setting the SMD bit of the standby control register (STBC) to IDLE or STOP mode and executing the HALT instruction. To enable DRAM to perform self-refresh, the standard RAS pulse width for DRAM (100 s or greater) must be ensured. Self-refresh is canceled using the RESET or NMI pin. The procedure for cancellation by RESET input is the same as that for normal reset. 6.2 ROM Controller (ROMC) The ROM controller supports access to ROM having a page access function (page-ROM). The ROM controller performs address comparison with the previous bus cycle and performs wait control for normal access (off-page)/page access (on-page). It supports page widths of 8-64 bytes. The page-ROM cycle is supported with address block 3. 6.2.1 on-page/off-page decision Whether the page-ROM cycle is on-page or off-page is determined by latching the address during the previous cycle and comparing it with the address during the current cycle. The address(es) (A3-A5) to be masked (not compared) is set using the page-ROM configuration register (PRC), according to the configuration of the connected page-ROM and the number of consecutively readable bits. 33 PD70741 Figure 6-2. on-page/off-page Decision When ROM Having a Page Access Function Is Connected (1) For 16-Mbit ROM (1-Mbit x 16) Internal address latch Setting of the PRC register V821 output address mrq a31 a30 (Same address block) Memory access Comparison Comparison a23 a22 a21 a20 a19 a18 a5 a4 a3 MA5 MA4 MA3 0 0 0 Comparison Comparison on/off-page A3 A2 A1 A0 MRQ a31 a30 (Internal) A23 A22 A21 A20 A19 A18 A5 A4 A'19 A'18 A'17 A'4 A'3 A'2 A'1 A'0 In-page address Consecutively readable bits: 16 bits x 4 (2) For 16-Mbit ROM (2-Mbit x 8) Internal address latch Setting of the PRC register V821 output address mrq a31 a30 (Same address block) Memory access Comparison Comparison a23 a22 a21 a20 a19 a18 a5 a4 a3 MA5 MA4 MA3 1 0 0 Comparison Comparison x on/off-page A3 A2 A1 A0 MRQ a31 a30 (Internal) A23 A22 A21 A20 A19 A18 A5 A4 A'19 A'18 A'17 A'4 A'3 A'2 A'1 A'0 A'-1 In-page address Consecutively readable bits: 8 bits x 8 34 PD70741 7. DMA FUNCTIONS (DMA CONTROLLER) The V821 includes a DMA (Direct Memory Access) controller that executes and controls DMA transfer. The DMAC (DMA controller) transfers data between memory and I/O, or within memory, based on DMA requests issued by the built-in peripheral hardware (serial interfaces and timer), external DREQ pins, or software triggers. 7.1 Features * * * * Two independent DMA channels Transfer units: 8/16 bits Maximum transfer count: 65 536 (216) Two types of transfer * Fly-by (one-cycle) transfer * Two-cycle transfer * Three transfer modes * Single transfer mode * Single-step transfer mode * Block transfer mode * Transfer requests * External DREQ pin (x 2) * Requests from built-in peripheral hardware (serial interfaces and timer) * Requests from software * Transfer objects * Memory to I/O and vice versa * Memory to memory and vice versa * Programmable wait function * DMA transfer end output signal (TC) 35 PD70741 Figure 7-1. Block Diagram of DMAC I/O Bus interface ROM External data bus Peripheral data bus Address control section DMA source address registers RAM Data control section Internal data bus DMA destination address registers I/O Count control section DMA byte count registers I/O Channel control section DMA channel control registers INTST INTDMA INTCM1 INTCSI INTSR TC DREQ 36 DACK PD70741 8. SERIAL INTERFACE FUNCTION 8.1 Features The V821 provides two transmission and reception channels as part of its serial interface function. The two interface modes listed below are supported, one channel being provided for each mode. The two modes operate independently of each other. (1) Asynchronous serial interface (UART) (2) Synchronous serial interface (CSI) In UART mode, one-byte serial data is transmitted or received after a start bit, and full-duplex communication is enabled. In CSI mode, data is transferred using three signal lines (three-wire serial I/O): the serial clock (SCLK), serial input (SI), and serial output (SO). 8.2 Asynchronous Serial Interface (UART) 8.2.1 Features Transfer rate 110 bps to 38 400 bps (when BRG is used with = 25 MHz) 781 Kbps maximum Full-duplex communication Two-pin configuration TXD : Transmission data output pin RXD : Reception data input pin Reception error detection function * Parity error * Framing error * Overrun error Interrupt source (3 types) * Reception error interrupt (INTSER) * Reception completion interrupt (INTSR) * Transmission completion interrupt (INTST) The character length for transmission and reception data is specified upon ASIM reception. Character length : 7 or 8 bits 9 bits (when an extended bit is used) Parity function: Odd parity, even parity, zero parity, without parity Transmission stop bit: 1 or 2 bits On-chip baud rate generator (when /2 is used with = 25 MHz) 37 PD70741 Figure 8-1. Block Diagram of Asynchronous Serial Interface Internal bus 16/8 8 16/8 ASIM SL SCLS Reception RXB buffer RXBL 8 ASIS RXD TXD Reception control parity check Reception shift register PE FE OVESOT RXE PS EBS CL Transmission shift register TXS TXSL INTSR Transmission INTSER control parity bit addition INTST 1 2 Selector 1 16 1 16 Baud rate generator 38 PD70741 8.3 Synchronous Serial Interface (CSI) 8.3.1 Features High-speed transfer 6.25 Mbps maximum (when /2 is used with = 25 MHz) Half-duplex communication Character length: 8 bits Switchable between the MSB and LSB to lead data transfer Allows selection between external serial clock input and internal serial clock output Three-wire method SO SI One interrupt source * Interrupt request signal (INTCSI) Figure 8-2. Block Diagram of Clock Synchronous Serial Interface : Serial data output : Serial data input SCLK : Serial clock I/O pin Internal bus CSIM CTXE CRXE SOT MOD CLS SO latch SI Shift register (SIO) D Q SO Selector SCLK Serial clock control circuit Selector 1 2 Baud rate generator /2 Serial clock counter Interrupt control circuit INTCSI 39 PD70741 8.4 Baud Rate Generator (BRG) 8.4.1 Configuration and function With the serial interface, a serial clock chosen from the baud rate generator output and clocks generated using the system clock () can be used as a baud rate. A serial clock source can be specified by using the SCLS bit of the ASIM register when the UART is used, or by using the CLS bit of the CSIM register when the CSI is used. When baud rate generator output is specified, the baud rate generator is selected as the clock source. The same serial clock is used for both transmission and reception on a channel, so that the same baud rate applies to transmission and reception. Figure 8-3. Block Diagram Internal bus 7 BRG 0 BPRM BRCE BPR Match UART Clear CSI 1 2 TMBRG Prescaler /2 40 PD70741 9. TIMER/COUNTER FUNCTIONS (REAL-TIME PULSE UNIT) The real-time pulse unit (RPU) measures pulse intervals and frequencies, and outputs programmable pulses. It is capable of 16-bit measurement. It can also generate various types of pulses, such as interval pulse and one-shot pulse. 9.1 Features Timer 0 (TM0) * 16-bit timer/event counter * Two count clock sources (system clock frequency division selected or external pulse input) * Four capture/compare registers * Count clear pin (TCLR) * Five interrupt sources * Two external pulse outputs Timer 1 (TM1) * 16-bit interval timer * Count clock generated by dividing the system clock frequency * Compare register * Interrupt source Figure 9-1. Timer 0 (16-Bit Timer/Event Counter) TCLR Edge detection Clear and start Clear and start /2 /4 TI m Note 2 m m/4 m/8 m/16 Note 1 TM0 (16 bits) INTOV0 Edge detection Edge detection Edge detection Edge detection Edge detection S INTCC00 INTCC01 CC00 CC01 CC02 CC03 Q TO00 RNote 3 Q S RNote 3 Q TO01 Q INTP00 INTP01 INTP02 INTP03 INTCC02 INTCC03 Notes 1. Internal count clock 2. External count clock 3. A reset takes precedence. Remark : System clock 41 PD70741 Figure 9-2. Timer 1 (16-Bit Interval Timer) /2 /4 /8 m m/16 Note m/32 TM1 (16 bits) Clear and start CM1 INTCM1 Note Internal count clock Remark : System clock 42 PD70741 10. WATCHDOG TIMER FUNCTIONS The watchdog timer is intended to prevent program crash and deadlock. 10.1 Features * The following three different time-out time values can be specified: 10.5 ms, 41.9 ms, and 167.8 ms (when system clock = 25 MHz) * Watchdog timer time-out output (WDTOUT) Figure 10-1. Watchdog Timer Block Diagram Frequency divider /210 /212 /214 Watchdog timer (8 bits) Time-out Active timer (5 bits) Clear Time-out R S Q WDTOUT WDTM register CLR bit RESET STOP Oscillation settling time control circuit Remark : System clock 43 PD70741 (1) Watchdog timer One of the watchdog timer functions is to secure the oscillation settling time of the system clock. When the system is reset or placed in STOP mode, the timer is cleared to 00H. The watchdog timer behaves in the standby modes as follows: (a) STOP mode The watchdog timer stops counting. When the system is released from STOP mode, the timer value is cleared. The watchdog timer starts counting at 00H, and keeps counting until a time-out occurs. A time-out signal is supplied to the oscillation settling time control circuit, thus starting to supply the system clock pulse. At this point, the WDTOUT pin does not become active. If the system is released from STOP mode by the NMI pin, the timer continues counting. (b) IDLE mode The watchdog timer stops counting, but it holds the count value. When the system is released from IDLE mode, the watchdog timer resumes counting by starting at the current count value. (c) HALT mode The watchdog timer continues counting. (2) Active timer The watchdog timer outputs the WDTOUT signal when it times out. The active timer retains this signal for 32 clock cycles. When the watchdog timer times out, it can cause a system reset by connecting the WDTOUT and RESET pins through an external circuit. 10.2 Operation The watchdog timer indicates that the program or system is running normally, by keeping the WDTOUT pin from becoming active. To use the watchdog timer, it is necessary to specify the WDTM register so that the watchdog timer is cleared (restarted to count) at constant intervals during program execution or at the beginning of a subroutine. If the watchdog timer expires because it is not cleared within a specified period of time, the WDTOUT pin becomes active, indicating a program failure. In addition, the WDT time-out flag (OV) is set. This flag is cleared by clearing the WDT counter. To use a watchdog timer time-out as an interrupt source, it is necessary to connect the WDTOUT pin to an external interrupt request pin (INTPn or NMI) through an external circuit. 44 PD70741 11. PORT FUNCTIONS The V821 pins are dual-function pins that can function as both port and control pins. See Chapter 1 for details of each pin. 11.1 Features * 10 input/output ports (P00 to P09) Figure 11-1. Configuration Write Mode (PMx) Internal address Latch I/O Read 45 PD70741 12. CLOCK GENERATION FUNCTIONS The clock generator generates and controls the internal clock pulse () for the CPU and other built-in hardware units. 12.1 Features Frequency multiplication (5 times) using a PLL (phase locked loop) synthesizer Clock sources * Resonator-based oscillation: fXX = /5 * External clock * External clock Clock output control Figure 12-1. Configuration : fXX = /5 (PLL mode) (PLL mode) : fXX = 2 x (direct mode) RESET Latch TCLR Direct mode (fXX) X1 (fXX) X2 OSC 1 2 PLL synthesizer (10 * fXX) PLL mode 1 2 CLKOUT STOP mode : Internal clock frequency ( = 1/2*10*fXX: PLL mode) Internal clock frequency ( = 1/2*fXX: Direct mode) OSC : Oscillator (only for the PLL mode) 46 PD70741 13. STANDBY FUNCTIONS The V821 supports three standby modes to suppress power dissipation. In these standby modes, the operation of the clock is controlled. The HALT instruction is used to select a standby mode. Mode switching is controlled using the standby control register. 13.1 Features HALT mode (Only the CPU clock stops.) IDLE mode (The CPU and peripheral operation clocks stop. The clock generator continues to operate.) STOP mode (The entire system, including the clock generator, stops.) 13.2 Standby Mode The standby modes of the V821 are detailed below. (1) HALT mode In this mode, the clock generator (oscillator and PLL synthesizer) continues operation, but the CPU clock stops. Clock supply to other built-in peripheral functions continues to allow them to keep running. Intermittent operation achieved using this standby mode in conjunction with the ordinary operation mode can reduce the total power dissipation of the system. (2) IDLE mode In this mode, the clock generator (oscillator and PLL synthesizer) continues operation, but internal system clock supply is stopped to bring the entire system to a stop. When the system is released from IDLE mode, it is unnecessary to secure oscillation settling time for the oscillator, and therefore it is possible for the system to shift to the ordinary operation quickly. For the oscillation settling time and current drain, IDLE mode lies in between STOP and HALT modes. IDLE mode is suitable for an application where it is necessary to cut the oscillation settling time using a low current drain mode. (3) STOP mode In this mode, the clock generator (oscillator and PLL synthesizer) is stopped to bring the entire system to a stop. This mode can generate an ultra-low power dissipation condition; only leak current occurs. (a) PLL mode In this mode, the PLL synthesizer clock output is stopped simultaneously with the oscillator. After the system is released from STOP mode, it is necessary to allow oscillation settling time for the oscillator. Some programs require a PLL lock-up time. (b) Direct mode In the direct mode, it is unnecessary to secure lock-up time. Table 13-1 lists the operation of the clock generator in the ordinary, HALT, IDLE, and STOP modes. An effective low power dissipation system can be implemented by combining and switching these modes. 47 PD70741 Table 13-1. Clock Generator Operation under Standby Control Clock source Standby mode Oscillator (OSC) PLL synthesizer Clock supply to the peripheral I/O o o x x o o x x o o x x Clock supply to the CPU PLL mode Resonatorbased oscillation Ordinary HALT IDLE STOP o o o x x x x x x x x x o o o x o o o x x x x x o x x x o x x x o x x x External clock Ordinary HALT IDLE STOP Direct mode Ordinary HALT IDLE STOP Remark o : Operating x : Stopped Table 13-2. Operation Status in HALT, IDLE, or STOP Mode Function Clock generator Internal system clock CPU I/O line Peripheral function Internal data A0-A23, UBE D0-D15 CS0-CS3 IORD, IOWR MWR/LMWR, UMWR REFRQ, RAS, LCAS, UCAS 1 (other than during CBR refresh)Note OperatingNote Clock output (when the clock output is not inhibited) CBR self-refreshNote CBR self-refresh Operating Operating Stopped Retained Operating Stopped Stopped HALT mode IDLE mode STOP mode Stopped All internal data, such as in CPU registers is retained. PC outputNote High impedance 1Note 1 PC output HLDRQ CLKOUT Stopped 1 Note High impedance when HLDAK = 0 48 PD70741 14. RESET FUNCTIONS Inputting a low level to the RESET pin triggers a system reset, thus initializing the on-chip hardware. When the RESET pin is driven from a low level to a high, the CPU starts program execution. The registers should be initialized in a program as required. 14.1 Features The reset pin is provided with a noise suppressor circuit based on an analog delay (60 to 300 ns). 14.2 Pin Functions Table 14-1 lists the state of the output from each pin during a system reset. The output state is retained during the entire reset period. After the RESET pin is kept at a low level for 30 clock cycles, if the HLDRQ signal is inactive, a memory read cycle is started to fetch an instruction. Even during a reset period (when the RESET pin is kept at a low level), activating the HLDRQ signal can place the bus on hold. The state of each pin with the bus put on hold during a reset is basically the same as that with the bus put on hold during a non-reset period. The HLDRQ signal should be kept inactive during a power-on reset. It is necessary to provide a pull-up or pull-down resistor to the pins that become high impedance during a reset. If no pull-up or pull-down resistor is provided to these pins, memory may be damaged when the pins are driven to high impedance. The CLKOUT pin supplies clock pulses even during a reset. Table 14-1. Output State of Each Pin during a Reset Pin A0-A23 D0-D15 P00/TCLR P01/DREQ0 P02/DACK0 P03/DREQ1 P04/DACK1 P05/SI P06/SO P07/SCLK P08/TXD/UBE P09/RXD/TC Operation state Not defined High impedance HLDAK MRD LMWR/WE UMWR IORD IOWR CS1-CS3 RAS LCAS UCAS CS0/REFRQ BLOCK/WDTOUT Low level Pin Operation state High level 49 PD70741 15. INSTRUCTION SET 15.1 Instruction Format The V821 instructions are formatted in either 16 bits or 32 bits. Examples of the 16-bit format instruction are binomial operation, control, and conditional branch; those for the 32-bit format are load/store, I/O manipulate, 16bit immediate, jump & link, and extended operations. Some instructions have an unused field. However, do not write a program that uses this field because it is reserved for future use. This unused field must be set to zeros. Instructions are stored in memory in the following manner. * The lower half of an instruction, that is, the half which includes bit 0, is stored at the lower address. * The higher half of an instruction, that is, the half which includes bit 15 or 31, is stored at the higher address. (1) reg-reg instruction format (Format I) This format consists of one 6-bit field to hold an operation code and two 5-bit fields to specify general-purpose registers as instruction's operands. 16-bit instructions use this format. 15 opcode 10 9 reg2 54 reg1 0 (2) imm-reg instruction format (Format II) This format consists of one 6-bit field to hold an operation code, one 5-bit field to hold an immediate data, and one field to specify a general-purpose register as an operand. 16-bit instructions use this format. 15 opcode 10 9 reg2 54 imm 0 (3) Conditional branch instruction format (Format III) This format consists of one 3-bit field to hold an operation code, one 4-bit field to hold a condition code, and one 9-bit field to hold a branch displacement (with its LSB masked to 0). 16-bit instructions use this format. 15 13 12 cond 98 disp 0 0 opcode 50 PD70741 (4) Intermediate jump instruction format (Format IV) This format consists of one 6-bit field to hold an operation code and one 26-bit field to hold a displacement (with its LSB masked to 0). 32-bit instructions use this format. 15 opcode 10 9 0 31 disp 16 0 (5) 3-operand instruction format (Format V) This format consists of one 6-bit field to hold an operation code, two fields to specify general-purpose registers as operands, and one 16-bit field to hold an immediate data. 32-bit instructions use this format. 15 opcode 10 9 reg2 54 reg1 0 31 imm 16 (6) Load/store instruction format (Format VI) This format consists of one 6-bit field to hold an operation code, two fields to specify a general-purpose register, and one 16-bit field to hold a displacement. 32-bit instructions use this format. 15 opcode 10 9 reg2 54 reg1 0 31 disp 16 (7) Extension instruction format (Format VII) This format consists of one 6-bit field to hold an operation code, two 5-bit fields to specify general-purpose registers as operands, and one 6-bit field to hold an sub-operation code. 32-bit instructions use this format. 15 opcode 10 9 reg2 54 reg1 0 31 sub-opcode 26 25 RFU 16 51 PD70741 15.2 Instruction Mnemonic (In Alphabetical Order) The list of mnemonics is shown below. This section lists the instructions incorporated in the V821 along with their operations. The instructions are listed in the instruction mnemonic's alphabetical order to allow users to use this section as a quick reference or dictionary. The conventions used in the list are shown below. Instruction mnemonic Operand (s) Format CY OV S Z Instruction function Legend ADD reg1, reg2 I * * * * Mnemonic of instruction Identifier of operand Instruction format (See Section 15.1.) Flag operation - Remains unchanged * Inverts the previous value 0 Changes to 0 1 Changes to 1 Identifier reg1 reg2 imm5 imm16 disp9 disp16 disp26 regID vector adr Description General-purpose register (Used as a source register) General-purpose register (Used mainly as a destination register and occasionally as a source register) 5-bit immediate 16-bit immediate 9-bit displacement 16-bit displacement 26-bit displacement System register number Trap handler address that corresponds to a trap vector 52 PD70741 Table 15-1. Instruction Mnemonics (In Alphabetical Order) (1/9) Instruction mnemonic ADD reg1, reg2 I * * * * Addition: Adds the word data in the reg2-specified register and the word data in the reg1-specified register, then stores the result into the reg2-specified register. Addition: Sign-extends the 5-bit immediate data to 32 bits, and adds the extended immediate data and the word data in the reg2-specified register, then stores the result into the reg2-specified register. Floating-point addition: Adds the single-precision floating-point data in the reg2-specified register and the single-precision floatingpoint data in the reg1-specified register, then restores the result into the reg2-specified register while changing flags according to the result. Addition: Sign-extends the 16-bit immediate data to 32 bits, and adds the extended immediate data and the word data in the reg1-specified register, then stores the result into the reg2-specified register. AND: Performs the logical AND operation on the word data in the reg2-specified register and the word data in the reg1-specified register, then stores the result into the reg2-specified register. Transfer after ANDing bit strings: Performs a logical AND operation on a source bit string and a destination bit string, then transfers the result to the destination bit string. AND: Sign-extends the 16-bit immediate data to 32 bits, and performs a logical AND operation on the extended immediate data and the word data in the reg1-specified register, then stores the result into the reg2-specified register. Transfer after NOTting a bit string then ANDing it with another bit string: Performs a logical AND operation on a destination bit string and the 1's complement of a source bit string, then transfers the result to the destination bit string. Conditional branch (if Carry): PC relative branch Conditional branch (if Equal): PC relative branch Conditional branch (if Greater than or Equal): PC relative branch Conditional branch (if Greater than): PC relative branch Operand (s) Format CY OV S Z Instruction function ADD imm5, reg2 II * * * * ADDF.S reg1, reg2 VII * 0 * * ADDI imm16, reg1, reg2 V * * * * AND reg1, reg2 I - 0 * * ANDBSU - II - - - - ANDI imm16, reg1, reg2 V - 0 0 * ANDNBSU - II - - - - BC disp9 III - - - - BE disp9 III - - - - BGE disp9 III - - - - BGT disp9 III - - - - 53 PD70741 Table 15-1. Instruction Mnemonics (In Alphabetical Order) (2/9) Instruction mnemonic BH disp9 III Conditional branch (if Higher): PC relative branch Conditional branch (if Lower): PC relative branch Conditional branch (if Less than or Equal): PC relative branch Conditional branch (if Less than): PC relative branch Conditional branch (if Negative): PC relative branch Conditional branch (if Not Carry): PC relative branch Conditional branch (if Not Equal): PC relative branch Conditional branch (if Not Higher): PC relative branch Conditional branch (if Not Lower): PC relative branch Conditional branch (if Not Overflow): PC relative branch Conditional branch (if Not Zero): PC relative branch Conditional branch (if Positive): PC relative branch Unconditional branch: PC relative branch Conditional branch (if Overflow): PC relative branch Conditional branch (if Zero): PC relative branch Inter-processor synchronization in a multi-processor system Comparison: Subtracts the word data in the reg1-specified register from that for reg2 for comparison, then changes flags according to the result. Comparison: Sign-extends the 5-bit immediate data to 32 bits, and subtracts the extended immediate data from the word data in the reg2-specified register for comparison, then changes flags according to the result. Floating-point comparison: Subtracts the single-precision floating-point data in the reg1-specified register from that for reg2 for comparison, then changes flags according to the result. Operand (s) Format CY OV S Z Instruction function BL disp9 III - - - - BLE disp9 III - - - - BLT disp9 III - - - - BN disp9 III - - - - BNC disp9 III - - - - BNE disp9 III - - - - BNH disp9 III - - - - BNL disp9 III - - - - BNV disp9 III - - - - BNZ disp9 III - - - - BP disp9 III - - - - BR disp9 III - - - - BV disp9 III - - - - BZ disp9 III - - - - CAXI disp16 [reg1], reg2 VI * * * * CMP reg1, reg2 I * * * * CMP imm5, reg2 II * * * * CMPF.S reg1, reg2 VII * 0 * * 54 PD70741 Table 15-1. Instruction Mnemonics (In Alphabetical Order) (3/9) Instruction mnemonic CVT.SW reg1, reg2 VII 0 * * Data conversion from floating-point to integer: Converts the single-precision floating-point data in the reg1-specified register into an integer data, then stores the result into the reg2-specified register while changing flags according to the result. Data conversion from integer to floating-point: Converts the integer data in the reg1-specified register into a single-precision floating-point data, then stores the result into the reg2-specified register while changing flags according to the result. Signed division: Divides the word data in the reg2-specified register by that for reg1 with their sign bits validated, then stores the quotient into the reg2-specified register and the remainder into r30. Division is performed so that the sign of the remainder matches that of the dividend. Floating-point division: Divides the single-precision floating-point data in the reg2-specified register by that for reg1, then stores the result into the reg2-specified register while changing flags according to the result. Unsigned division: Divides the word data in the reg2-specified register by that for reg1 with their data handled as unsigned data, then stores the quotient into the reg2-specified register and the remainder into r30. Division is performed so that the sign of the remainder matches that of the dividend. Processor stop Port input: Sign-extends the 16-bit displacement to 32 bits, and adds the extended displacement and the content of the reg1-specified register to generate a 32-bit unsigned port address, then reads the byte data located at the generated port address, zero-extends the byte data to 32 bits, and stores the result into the reg2-specified register. Port input: Sign-extends the 16-bit displacement to 32 bits, and adds the extended displacement and the content of the reg1-specified register to generate a 32-bit unsigned port address, then reads the halfword data located at the generated port address while masking the address's bit 0 to 0, zero-extends the halfword data to 32 bits, and stores the result into the reg2-specified register. Operand (s) Format CY OV S Z Instruction function CVT.WS reg1, reg2 VII * 0 * * DIV reg1, reg2 I - * * * DIVF.S reg1, reg2 VII * 0 * * DIVU reg1, reg2 I - 0 * * HALT IN.B disp16 [reg1], reg2 II VI - - - - IN.H disp16 [reg1], reg2 VI - - - - 55 PD70741 Table 15-1. Instruction Mnemonics (In Alphabetical Order) (4/9) Instruction mnemonic IN.W disp16 [reg1], reg2 VI Port input: Sign-extends the 16-bit displacement to 32 bits, and adds the extended displacement and the content of the reg1-specified register to generate a 32-bit unsigned port address, then reads the word data located at the generated address while masking the address's bits 0 and 1 to 0, and stores the word into the reg2specified register. Jump and link: Increments the current PC by 4, then saves it into r31, and sign-extends the 26-bit displacement to 32 bits while masking the displacement's bit 0 to 0, adds the extended displacement and the PC value, loads the PC with the addition result, so that the instruction stored at the PC-pointing address is executed next. Register-indirect unconditional branch: Loads the PC with the jump address value in the reg1specified register while masking the value's bit 0 to 0, so that the instruction stored at the address pointed by the reg1-specified register is executed next. Unconditional branch: Sign-extends the 26-bit displacement to 32 bits while masking bit 0 to 0, adds the result with the current PC value, and loads the PC with the addition result so that the instruction stored at the PC-pointing address is executed next. Byte load: Sign-extends the 16-bit displacement to 32 bits, and adds the result with the content of the reg1-specified register to generate the 32-bit unsigned address, then reads the byte data located at the generated address, sign-extends the byte data to 32 bits, and stores the result into the reg2-specified register. Halfword load: Sign-extends the 16-bit displacement to 32 bits, and adds the result with the content of the reg1-specified register to generate a 32-bit unsigned address while masking its bit 0 to 0, then reads the halfword data located at the generated address, sign-extends the halfword data to 32 bits, and stores the result into the reg2-specified register. Word load: Sign-extends the 16-bit displacement to 32 bits and adds the result with the content of the reg1-specified register to generate a 32-bit unsigned address while masking bits 0 and 1 to 0, then reads the word data located at the generated address and stores the data into the reg2-specified register. Operand (s) Format CY OV S Z Instruction function JAL disp26 IV - - - - JMP [reg1] I - - - - JR disp26 IV - - - - LD.B disp16 [reg1], reg2 VI - - - - LD.H disp16 [reg1], reg2 VI - - - - LD.W disp16 [reg1], reg2 VI - - - - 56 PD70741 Table 15-1. Instruction Mnemonics (In Alphabetical Order) (5/9) Instruction mnemonic LDSR reg2, regID II * * * * Loading system register: Transfers the word data in the reg2-specified register to the system register specified with the system register number (regID). Transferring data: Loads the reg2-specified register with the word data in of the reg1-specified register. Transferring data: Sign-extends the 5-bit immediate data to 32 bits, then loads the reg2-specified register with the extended immediate data. Transferring bit strings: Loads the destination bit string with the source bit string. Addition: Sign-extends the 16-bit immediate data to 32 bits, adds it with the word data in the reg1-specified register, then stores the addition result into reg2. Addition: Appends 16-bit zeros below the 16-bit immediate data to form a 32-bit word data, then adds it with the word data in the reg1-specified register, and stores the result into the reg2-specified register. Signed multiplication: Signed-multiplies the word data in the reg2-specified register by that for reg1, then separates the 64-bit (double-word) result into two 32-bit data, and stores the higher 32 bits into r30 and the lower 32 bits into the reg2-specified register. Floating-point multiplication: Multiplies the single-precision floating-point data in the reg2-specified register by that for reg1, then stores the result into the reg2-specified register while changing flags according to the result. Unsigned multiplication: Multiplies the word data in the reg2-specified register by that for reg1 while handling these data as unsigned data, then separates the 64-bit (double-word) result into two 32-bit data, and stores the higher 32 bits into r30 and the lower 32 bits into the reg2-specified register. No operation Logical NOT: Obtains the 1's complement (logical NOT) of the content of the reg1-specified register, then stores the result into the reg2-specified register. Operand (s) Format CY OV S Z Instruction function MOV reg1, reg2 I - - - - MOV imm5, reg2 II - - - - MOVBSU - II - - - - MOVEA imm16, reg1, reg2 V - - - - MOVHI imm16, reg1, reg2 V - - - - MUL reg1, reg2 I - * * * MULF.S reg1, reg2 VII * 0 * * MULU reg1, reg2 I - * * * NOP NOT reg1, reg2 III I - 0 * * 57 PD70741 Table 15-1. Instruction Mnemonics (In Alphabetical Order) (6/9) Instruction mnemonic NOTBSU II Transfer after NOTting a bit string: Obtains the 1's complement (all bits inverted) of the source bit string, then transfers the result to the destination bit string. OR: Performs a logical OR operation on the word data in the reg2-specified register and that for reg1, then stores the result into the reg2-specified register. Transfer after ORing bit strings: Performs a logical OR operation on the source and destination bit strings, then transfers the result to the destination bit string. OR: Zero-extends the 16-bit immediate data to 32 bits, performs a logical OR operation on the extended data and the word data in the reg1-specified register, then stores the result into the reg2-specified register. Transfer after NOTting a bit string and ORing it with another bit string: Obtains the 1's complement (logical NOT) of the source bit string, performs a logical OR operation on the NOTted bit string and the destination bit string, then transfers the result to the destination bit string. Port output: Sign-extends the 16-bit displacement to 32 bits, adds the extended value and the content of the reg1specified register to generate a 32-bit unsigned port address, then outputs the lowest 8 bits (= 1 byte) of the reg2-specified register onto the port pins corresponding to the generated port address. Port output: Sign-extends the 16-bit displacement to 32 bits, adds the extended value and the content of the reg1specified register to generate a 32-bit unsigned port address with its bit 0 masked to 0, then outputs the lowest 16 bits (= 1 halfword) of the reg2-specified register onto the port pins corresponding to the generated port address. Port output: Sign-extends the 16-bit displacement to 32 bits, adds the extended value and the content of the reg1specified register to generate a 32-bit unsigned port address with its bits 0 and 1 masked to 0, then outputs the 32 bits (= 1 word) of the reg2-specified register onto the port pins corresponding to the generated port address. Operand (s) Format CY OV S Z Instruction function OR reg1, reg2 I - 0 * * ORBSU - II - - - - ORI imm16, reg1, reg2 V - 0 * * ORNBSU - II - - - - OUT.B reg2, disp16 [reg1] VI - - - - OUT.H reg2, disp16 [reg1] VI - - - - OUT.W reg2, disp16 [reg1] VI - - - - 58 PD70741 Table 15-1. Instruction Mnemonics (In Alphabetical Order) (7/9) Instruction mnemonic RETI II * * * * Return from a trap or interrupt routine: Reads the restore PC and PSW from the system registers and loads them to the due places to return from a trap or interrupt routine to the original operation flow. Arithmetic right shift: Shifts every bit of the word data in the reg2-specified register to the right by the number of times specified with the reg1-specified register's lowest 5 bits, then stores the result into the reg2-specified register. In arithmetic right shift operations, the MSB is loaded with the LSB value at each shift. Arithmetic right shift: Zero-extends the 5-bit immediate data to 32 bits, shifts every bit of the word data in the reg2-specified register to the right by the number of times specified with the extended immediate data, then stores the result into the reg2-specified register. Searching 0s in a bit string: Searches "0" bits in the source bit string, and loads r30 and r27 with the address of the bit next to the first detected "0" bit, then r29 with the number of bits skipped until the first "0" bit is detected, and r28 with the value subtracted by the r29 value. Searching 1s in a bit string: Searches 1s in the source bit string, and loads r30 and r27 with the bit address next to the first detected "1" bit, then r29 with the number of bits skipped until the first "1" is detected, and r28 with the value subtracted by the r29 value. Flag condition setting: Sets the reg2-specified register to 1 if the condition flag value matches the lowest 4 bits of the 5-bit immediate data, and sets the reg2-specified register to 0 when they do not match. Logical left shift: Shifts every bit of the word data in the reg2-specified register to the left by the number of times specified with the reg1-specified register's lowest 5 bits, then stores the result into the reg2-specified register. In logical left shift operations, the LSB is loaded with 0 at each shift. Operand (s) Format CY OV S Z Instruction function SAR reg1, reg2 I * 0 * * SAR imm5, reg2 II * 0 * * SCH0BSU SCH0BSD - II II - - - * * SCH1BSU SCH1BSD - II II - - - - SETF imm5, reg2 II - - - - SHL reg1, reg2 I * 0 * * 59 PD70741 Table 15-1. Instruction Mnemonics (In Alphabetical Order) (8/9) Instruction mnemonic SHL imm5, reg2 II * 0 * * Logical left shift: Zero-extends the 5-bit immediate data to 32 bits, shifts every bit of the word data in the reg2-specified register to the left by the number of times specified by the extended immediate data, then stores the result into the reg2-specified register. Logical right shift: Shifts every bit of the word data in the reg2-specified register to the right by the number of times specified with the reg1-specified register's lowest 5 bits, then stores the result into the reg2-specified register. In logical right shift operations, the MSB is loaded with 0 at each shift. Logical right shift: Zero-extends the 5-bit immediate data to 32 bits, shifts every bit of the word data in the reg2-specified register to the right by the number of times specified by the extended immediate data, then stores the result into the reg2-specified register. Byte store: Sign-extends the 16-bit displacement to 32 bits and adds the 32-bit displacement and the content of the reg1-specified register to generate a 32-bit unsigned address, then transfers the reg2-specified register's lowest 8 bits to the generated address. Halfword store: Sign-extends the 16-bit displacement to 32 bits with its bit 0 masked to 0, and adds the content of the reg1specified register and the 32-bit displacement to generate a 32-bit unsigned address, then transfers the reg2specified register's lower 16 bits to the generated address. Word store: Sign-extends the 16-bit displacement to 32 bits with its bits 0 and 1 masked to 0, and adds the reg1specified register and the 32-bit displacement to generate a 32-bit unsigned address, then transfers the word data of the reg2-specified register to the generated address. Storing system register contents: Loads the reg2-specified register with the content of the system register specified by the system register number (regID). Subtraction: Subtracts the word data in the reg1-specified register from that in the reg2-specified register, then stores the result into the reg2-specified register. Operand (s) Format CY OV S Z Instruction function SHR reg1, reg2 I * 0 * * SHR imm5, reg2 II * 0 * * ST.B reg2, disp16 [reg1] VI - - - - ST.H reg2, disp16 [reg1] VI - - - - ST.W reg2, disp16 [reg1] VI - - - - STSR regID, reg2 II - - - - SUB reg1, reg2 I * * * * 60 PD70741 Table 15-1. Instruction Mnemonics (In Alphabetical Order) (9/9) Instruction mnemonic SUBF.S reg1, reg2 VII * 0 * * Floating-point subtraction: Subtracts the single-precision floating-point data in the reg1-specified register from that for reg2, then stores the result into the reg2-specified register while changing flags according to the result. Software trap: Jumps to a trap handler address according to the vector-specified trap vector (from 0 to 31) to start an exception handling after completing all necessary saving and presetting procedures as follows: (1) Saving the restore PC and PSW into the FEPC and FEPSW system registers, respectively, if the PSW's EP flag = 1, or into the EIPC and EIPSW system registers, respectively, if EP = 0 (2) Setting an exception code into the ECR's FECC and FEPSW flags if the PSW's EP flag = 1, or into the ECR's EICC if EP = 0 (3) Setting the PSW's ID flag and clearing the PSW's AE flag (4) Setting the PSW's NP flag if the PSW's EP flag = 1, or setting the PSW's ID flag if EP = 0 Conversion from floating-point data to integer: Converts the single-precision floating-point data in the reg1-specified register into an integer data, then stores the result into the reg2-specified register while changing flags according to the result. Exclusive OR: Performs a logical exclusive-OR operation on the word data in the reg2-specified register and that for reg1, then stores the result into the reg2-specified register. Transfer of exclusive ORed bit string: Performs a logical exclusive-OR operation on the source and destination bit strings, then transfers the result to the destination bit string. Exclusive OR: Zero-extends the 16-bit immediate data to 32 bits and performs a logical exclusive-OR operation on the extended immediate data and the word data in the reg1-specified register, then stores the result into the reg2-specified register. Transfer after exclusive-ORing a NOTted bit string and another bit string: Obtains the 1's complement (NOT) of the source bit string, and exclusive-ORs it with the destination bit string, then transfers the result to the destination bit string. Operand (s) Format CY OV S Z Instruction function TRAP vector II - - - - TRNC.SW reg1, reg2 VII - 0 * * XOR reg1, reg2 I - 0 * * XORBSU - II - - - - XORI imm16, reg1, reg2 V - 0 * * XORNBSU - II - - - - 61 PD70741 16. ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS (TA = 25 C) Parameter Supply voltage Input voltage Clock input voltage Output voltage Operating ambient temperature Storage temperature Symbol VDD VI VK VO TA Tstg VDD = +5.0 V 10 % VDD = +5.0 V 10 % VDD = +5.0 V 10 % Conditions Rating -0.5 to +7.0 -0.5 to VDD + 0.3 -0.5 to VDD + 0.3 -0.5 to VDD + 0.3 -40 to +85 -65 to +150 Unit V V V V C C Cautions 1. Do not connect an output (or input/output) pin of an IC device directly to any other output (or input/output) pin of the same device, or directly to VDD , VCC, or GND. Open-drain pins and open-collector pins can, however, be connected directly to each other. Note, however, that these restrictions do not apply to those high-impedance pins that are provided with an external circuit for which timings have been designed such that no output contention occurs. 2. Absolute maximum ratings are rated values beyond which some physical damages may be caused to the product; if any of the parameters in the table above exceeds its rated value even for a moment, the quality of the product may deteriorate. Be sure to use the product with a moderate value within the rated range. The standard values and conditions listed in the DC and AC characteristics tables indicate the ranges in which the normal operation and performance of the product can be guaranteed. DC CHARACTERISTICS (TA = -40 to +85 C, VDD = +5.0 V 10 %) Parameter Low-level clock input voltage High-level clock input voltage Low-level input voltage Symbol VKL VKH VIL1 VIL2 High-level input voltage VIH1 VIH2 Schmitt-triggered input hysteresis width VSH Low-level output voltage High-level output voltage VOL VOH Other than RESET, NMI, and INTPn RESET, NMI, and INTPn Other than RESET, NMI, and INTPn RESET, NMI, and INTPn RESET, NMI, and INTPn IOL = 2.5 mA IOH = -2.5 mA IOH = -100 A Low-level input leakage current High-level input leakage current Low-level output leakage current High-level output leakage current Supply current ILIL ILIH ILOL ILOH IDD VIN = 0 V VIN = VDD VO = 0 V VO = VDD Operation (f = 25 MHz) HALT (f = 25 MHz) IDLE (f = 25 MHz) STOP 100 18 4 5 0.7VDD VDD - 0.4 -10 10 -10 10 150 45 35 20 Conditions MIN. -0.5 4.0 -0.5 -0.5 2.2 0.8VDD 0.5 0.45 TYP. MAX. +0.6 VDD + 0.3 +0.8 +0.2VDD VDD + 0.3 VDD + 0.3 Unit V V V V V V V V V V A A A A mA mA mA A 62 PD70741 CAPACITANCE (TA = 25 C, VDD = +5.0 V 10 %) Parameter Input capacitance Input/output capacitance Symbol CI CIO Conditions fc = 1 MHz MIN. MAX. 15 15 Unit pF pF 63 PD70741 AC CHARACTERISTICS (TA = -40 to +85 C, VDD = +5.0 V 10 %) AC Test Input Waveform (Other than RESET, NMI, and INTPn) Parameter Input rise time Input fall time 1 2 Symbol tR tF Conditions MIN. MAX. 7 7 Unit ns ns VDD 2.2 V 0.8 V 2 Test points 2.2 V 0.8 V 1 0V AC Test Input Waveform (RESET, NMI, and INTPn) Parameter Schmitt-triggered input rise time Schmitt-triggered input fall time 3 4 Symbol tRS tFS Conditions MIN. MAX. 10 10 Unit ns ns VDD 0.8VDD 0.8 V 4 Test points 0.8VDD 0.8 V 3 0V AC Test Output Waveform 2.2 V 0.8 V Test points 2.2 V 0.8 V Load Condition V821 output pin CL = 100 pF 64 PD70741 RECOMMENDED OSCILLATION CIRCUIT (a) Connecting a ceramic resonator (Murata Mfg. Co., Ltd.: TA = -20 to +80 C, TDK Corp.: TA = -40 to +85 C) X1 X2 C1 C2 Cautions 1. The oscillation circuit should be placed as close to the X1 and X2 pins as possible. 2. Do not draw other signal lines in the area enclosed by broken lines. 3. Throughly evaluate the matching between the PD70741 and the oscillation circuit. Manufacturer Product name Oscillation frequency fxx (MHz) 5.00 5.00 4.00 4.00 3.20 Recommended circuit constants C1 (pF) 30 Built-in 30 Built-in 30 C2 (pF) 30 Built-in 30 Built-in 30 Oscillating voltage range MIN. (V) 4.5 4.5 4.5 4.5 2.7 4.5 CST3.20MGW 3.20 Built-in Built-in 2.7 4.5 CSA2.00MG040 2.00 100 100 2.7 4.5 CST2.00MG040 2.00 Built-in Built-in 2.7 4.5 TDK CCR5.0MC3 FCR5.0MC5 CCR4.0MC3 FCR4.0MC5 CCR3.2MC3 CCR2.0MC33 5.00 5.00 4.00 4.00 3.20 2.00 Built-in Built-in Built-in Built-in Built-in Built-in Built-in Built-in Built-in Built-in Built-in Built-in 4.5 4.5 4.5 4.5 2.7 2.7 MAX. (V) 5.5 5.5 5.5 5.5 3.3 5.5 3.3 5.5 3.3 5.5 3.3 5.5 5.5 5.5 5.5 5.5 5.5 5.5 Oscillation settling time (MAX.) TOST (ms) 0.102 0.102 0.1 0.1 0.102 0.102 0.102 0.102 0.498 0.498 0.498 0.498 0.28 0.22 0.3 0.22 0.38 0.36 Murata Mfg. Co., Ltd CSA5.00MG CST5.00MGW CSA4.00MG CST4.00MGW CSA3.20MG 65 PD70741 (b) External clock input X1 X2 Open High-speed CMOS inverter External clock 66 PD70741 (1) Clock input timing Parameter External clock cycle 5 Symbol tCYX Conditions Direct mode PLL mode MIN. 20 200 7 85 7 85 MAX. Unit ns 500 ns ns ns ns ns External clock high-level width 6 tXKH Direct mode PLL mode External clock low-level width 7 tXKL Direct mode PLL mode External clock rise time 8 tXKR Direct mode PLL mode 3 15 3 15 ns ns ns ns External clock fall time 9 tXKF Direct mode PLL mode 5 6 9 8 2.2 V X1 (input) 0.8 V 7 (2) CLKOUT output timing Parameter CLKOUT cycle CLKOUT high-level width CLKOUT low-level width CLKOUT rise time (0.8 V 2.2 V) CLKOUT fall time (2.2 V 0.8 V) 10 11 12 Symbol tCYK tKKH tKKL tKR tKF Conditions MIN. 40 0.5T - 3 0.5T - 3 MAX. 100 Unit ns ns ns 13 14 5 5 ns ns Remark T: tCYK 10 11 14 13 2.2 V CLKOUT (output) 0.8 V 12 67 PD70741 (3) Reset input timing Parameter Reset input width 15 Symbol tWRL Conditions Power-on reset STOP mode release System reset MIN. 10 10 MAX. Unit ms ms 30 tCYK 15 RESET (input) 68 PD70741 [MEMO] 69 PD70741 (4) SRAM, ROM, and I/O access timing (a) Access timing (1/2) Parameter Address output delay (relative to CLKOUT) Address output hold time (relative to CLKOUT) CSn output delay (relative to CLKOUT) CSn output hold time (relative to CLKOUT) RD output delay (relative to CLKOUT) RD output hold time (relative to CLKOUT) WR output delay (relative to CLKOUT) WR output hold time (relative to CLKOUT) READY setup time (relative to CLKOUT) READY hold time (relative to CLKOUT) Data output delay (from float, relative to CLKOUT) Data output hold time (to float, relative to CLKOUT) 16 17 18 Symbol tDKA tHKA tDKCS tHKCS tDKRD tHKRD tDKWR tHKWR tSRYK tHKRY tLZKDT tHZKDT Conditions MIN. 2 2 2 2 2 2 1 1 6 6 2 2 MAX. 15 15 15 15 15 15 12 12 Unit ns ns ns ns ns ns ns ns ns ns 19 20 21 22 23 24 25 26 27 15 15 ns ns 70 PD70741 (a) Access timing (2/2) T1 CLKOUT (output) 16 T2 T2 17 Note 18 19 CS0-CS3 (output) 20 21 IORD, MRD (output) 22 23 IOWR, UMWR, LMWR (output) 24 25 24 25 READY (input) 26 27 D0-D15 (input/output) (ADC = 0) (write) 26 27 D0-D15 (input/output) (ADC = 1) (write) Note A0-A23 (output), UBE (output), BLOCK (output) Remark Broken lines indicate high impedance. 71 PD70741 (b) Read timing (1/2) Parameter Read cycle time Address access time Hold time from address to data input CSn access time Hold time from CSn to data input Delay from CSn to write data output (ADC = 0) Delay from CSn to write data output (ADC = 1) RD access time Hold time from RD to data input RD pulse width RD high-level width Delay from RD to write data output (ADC = 0) Delay from RD to write data output (ADC = 1) Address valid time prior to RD CSn valid time prior to RD 28 Symbol tRC tAA tADH tCSA tCDH tDCD0 tDCD1 tRDA tRDH tRDP tRDRDH tDRD0 tDRD1 tARS tCRS Conditions MIN. (n + 2)T - 10 MAX. Unit ns 29 30 31 (n + 2)T - 25 0 (n + 2)T - 25 0 0.5T - 10 1T - 10 (n + 1.5)T - 25 0 (n + 1.5)T - 7 0.5T - 10 0.5T - 10 1T - 10 0.5T - 7 0.5T - 7 ns ns ns ns ns ns ns ns ns ns ns ns ns ns 32 33 34 35 36 37 38 39 40 41 42 Remark T : tCYK n : Wait state count 72 PD70741 (b) Read timing (2/2) T1 CLKOUT (output) 28 29 T2 30 A0-A23, UBE (output) 41 31 32 33 34 CS0-CS3 (output) 42 35 37 36 38 IORD, MRD (output) 39 40 D0-D15 (input/output) (ADC = 0) D0-D15 (input/output) (ADC = 1) Remark Broken lines indicate high impedance. 73 PD70741 (c) Write timing (1/2) Parameter Write cycle time CSn setup time (relative to WR) Address setup time (relative to WR) Address valid time prior to WR Address valid time after WR CSn valid time prior to WR CSn valid time after WR WR pulse width Delay from WR to data output (ADC = 0) Delay from WR to data output (ADC = 1) Data output valid time prior to WR (ADC = 0) Data output valid time prior to WR (ADC = 1) Data output valid time after WR 43 Symbol tWC tCW tAW tAWS tAWH tCWS tCWH tWRP tWDS0 tWDS1 tDWS0 tDWS1 tDWH Conditions MIN. (n + 2)T - 10 (n + 1.5)T - 10 (n + 1.5)T - 10 0.5T - 7 0.5T - 10 0.5T - 7 0.5T - 10 (n + 1)T - 7 -10 0.5T - 10 (n + 1)T - 7 (n + 0.5)T - 7 0.5T - 10 MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns 44 45 46 47 48 49 50 51 52 53 54 55 Remark T : tCYK n : Wait state count 74 PD70741 (c) Write timing (2/2) T1 CLKOUT (output) 43 46 T2 47 A0-A23, UBE (output) 45 48 49 CS0-CS3 (output) 44 50 IOWR, UMWR, LMWR (output) 51 53 55 D0-D15 (input/output) (ADC = 0) 52 54 55 D0-D15 (input/output) (ADC = 1) Remark Broken lines indicate high impedance. 75 PD70741 (5) DRAM access timing (when DRAM is directly connected) (a) Read timing (normal access: off-page) (1/2) Parameter Delay from RD to write data output (ADC = 0) Delay from RD to write data output (ADC = 1) Read/write cycle time RAS access time CAS access time Access time from column address Output enable access time Output buffer turn-off delay (relative to CAS) Output buffer turn-off delay (relative to MRD) RD setup time (relative to RAS) RAS precharge time RAS pulse width RAS column address delay RAS hold width (read) CAS pulse width (read) CAS hold width RAS-CAS delay (read) RAS-CAS precharge time CAS precharge time Row address setup time Row address hold time Column address setup time (read) Column address hold time (read) Column address read time relative to RAS Read command setup time Read command hold time 39 40 56 Symbol tDRD0 tDRD1 tRC tRAC tCAC tAA tOEA tOFF tOEZ tOES tRP tRAS tRAD tRSH tCAS tCSH tRCD tCRP tCP tASR tRAH tASC tCAH tRAL tRCS tRCH Conditions MIN. 0.5T - 10 1T - 10 (w + 4)T - 10 MAX. Unit ns ns ns 57 58 59 (w + 2)T - 20 (w + 1)T - 20 (w + 1)T - 3 1.5T - 20 0 0 1.5T 1.5T - 10 (w + 2.5)T - 20 0.5T - 3 (w + 1.5)T - 20 (w + 1)T - 15 (w + 2)T - 15 1T - 15 1.5T 0.5T - 10 0.5T - 15 0.5T - 7 0.5T - 15 (w + 1)T - 15 (w + 1.5)T 0.5T 0.5T - 15 0.5T + 7 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 Remark T : tCYK w : Wait state count - 2 76 PD70741 (a) Read timing (normal access: off-page) (2/2) T1 CLKOUT (output) T2 T2 T2 73 74 75 76 A0-A23, UBE (output) COL. ROW 56 64 COL. 65 RAS (output) 67 71 70 69 68 72 UCAS, LCAS (output) 66 78 77 79 WE (output) 61 58 59 60 MRD (output) 63 39 D0-D15 (input/output) (ADC = 0) 62 57 40 D0-D15 (input/output) (ADC = 1) Remark Broken lines indicate high impedance. 77 PD70741 (b) Write timing (normal access: off-page) (1/2) Parameter Read/write cycle time RAS precharge time RAS pulse width RAS column address delay CAS hold width RAS-CAS precharge time Row address setup time Row address hold time Column address read time relative to RAS RAS hold width (write) CAS pulse width (write) RAS-CAS delay (write) Column address setup time (write) Column address hold time (write) Write command hold time Write command read time relative to RAS Write command read time relative to CAS Data setup time (relative to CAS) Data hold time (relative to CAS) Write command setup time 56 Symbol tRC tRP tRAS tRAD tCSH tCRP tASR tRAH tRAL tRSH tCAS tRCD tASC tCAH tWCH tRWL tCWL tDS tDH tWCS Conditions MIN. (w + 4)T - 10 1.5T - 10 (w + 2.5)T - 20 0.5T - 3 (w + 2)T - 15 1.5T 0.5T - 15 0.5T - 7 (w + 1.5)T 1.5T - 20 1T - 15 (w + 1)T - 15 (w + 0.5)T - 15 1T - 15 0.5T - 10 1.5T 1T 0.5T - 15 1T - 20 0.5T - 15 MAX. Unit ns ns ns 64 65 66 0.5T + 7 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 69 71 73 74 77 80 81 82 83 84 85 86 87 88 89 1T + 10 ns ns 90 Remark T : tCYK w : Wait state count - 2 78 PD70741 (b) Write timing (normal access: off-page) (2/2) T1 T2 T2 T2 CLKOUT (output) 73 74 83 84 A0-A23, UBE (output) COL. 64 ROW 56 66 COL. 65 77 RAS (output) 80 71 82 69 81 UCAS, LCAS (output) 90 85 WE (output) 87 86 MRD (output) 88 89 D0-D15 (input/output) (ADC = 0) 88 89 D0-D15 (input/output) (ADC = 1) Remark Broken lines indicate high impedance. 79 PD70741 (c) READY input timing (normal access) Parameter READY setup time (relative to CLKOUT) READY hold time (relative to CLKOUT) 24 Symbol tSRYK tHKRY Conditions MIN. 6 6 MAX. Unit ns ns 25 T2 CLKOUT (output) T2 T2 UCAS, LCAS (output) (read) UCAS, LCAS (output) (write) 24 25 24 25 READY (input) 80 PD70741 [MEMO] 81 PD70741 (d) Read timing (high-speed page access: on-page) (1/2) Parameter Delay from RD to write data output (ADC = 0) Delay from RD to write data output (ADC = 1) CAS access time Access time from column address Output enable access time Output buffer turn-off delay (relative to CAS) Output buffer turn-off delay (relative to MRD) RD setup time (relative to RAS) RAS hold width (read) CAS pulse width (read) CAS precharge time Column address setup time (read) Column address hold time (read) Cycle time in high-speed page mode Access time from CAS precharge RAS hold time relative to CAS precharge Read command setup time Read command hold time 39 40 Symbol tDRD0 tDRD1 tCAC tAA tOEA tOFF tOEZ tOES tRSH tCAS tCP tASC tCAH tPC tACP tRHCP tRCS tRCH Conditions MIN. 0.5T - 10 1T - 10 MAX. Unit ns ns 58 59 60 (w + 1)T - 20 (w + 1)T - 3 1.5T - 20 0 0 1.5T (w + 1.5)T - 20 (w + 1)T - 15 0.5T - 10 0.5T - 15 (w + 1)T - 15 1.5T - 10 2T - 20 2T 0.5T 0.5T - 15 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 61 62 63 67 68 72 75 76 91 92 93 94 95 Remark T : tCYK w:0 82 PD70741 (d) Read timing (high-speed page access: on-page) (2/2) T1 CLKOUT (output) T2 75 76 A0-A23, UBE (output) COL. 93 67 RAS (output) 72 68 91 UCAS, LCAS (output) 94 58 95 WE (output) 59 92 63 61 MRD (output) 39 40 D0-D15 (input/output) (ADC = 0) 60 62 D0-D15 (input/output) (ADC = 1) Remark Broken lines indicate high impedance. 83 PD70741 (e) Write timing (high-speed page access: on-page) (1/2) Parameter CAS precharge time RAS hold width (write) CAS pulse width (write) Column address setup time (write) Column address hold time (write) Write command hold time Write command read time relative to RAS Write command read time relative to CAS Data setup time (relative to CAS) Data hold time (relative to CAS) Write command setup time Cycle time in high-speed page mode 72 80 Symbol tCP tRSH tCAS tASC tCAH tWCH tRWL tCWL tDS tDH tWCS tPC Conditions MIN. 0.5T - 10 1.5T - 20 1T - 15 (w + 0.5)T - 15 1T - 15 0.5T - 10 1.5T 1T 0.5T - 15 1T - 20 0.5T - 15 1.5T - 10 MAX. Unit ns ns ns ns ns ns ns ns ns 81 83 84 85 86 87 88 89 90 1T + 10 ns ns ns 91 Remark T : tCYK w:0 84 PD70741 (e) Write timing (high-speed page access: on-page) (2/2) Note 1 T1 CLKOUT (output) 83 84 Note 2 T2 T1 T2 T2 83 84 A0-A23, UBE (output) COL. COL. 80 RAS (output) 91 81 72 81 UCAS, LCAS (output) 85 90 90 85 WE (output) 87 86 87 MRD (output) 88 88 89 89 D0-D15 (input/output) Notes 1. When ADC = 1 and other than DRAM access was performed in the previous cycle 2. Other than the above Remark Broken lines indicate high impedance. 85 PD70741 (6) DRAM access timing (when a control circuit is configured using a gate array or other devices) (a) Read timing (normal access: off-page) (1/2) Parameter Address output delay (relative to CLKOUT) Address output hold time (relative to CLKOUT) RAS output delay (relative to CLKOUT) RAS output hold time (relative to CLKOUT) CAS output delay (relative to CLKOUT) CAS output hold time (relative to CLKOUT) MRD output delay (relative to CLKOUT) MRD output hold time (relative to CLKOUT) Data input setup time (relative to CLKOUT) Data input hold time (relative to CLKOUT) 96 97 98 99 100 Symbol tDKA tHKA tDKRAS tHKRAS tDKCAS tHKCAS tDKRD tHKRD tSDK tHKD Conditions MIN. 2 2 1 1 1 1 2 2 6 6 MAX. 15 15 12 12 12 12 15 15 Unit ns ns ns ns ns ns ns ns ns ns 101 102 103 104 105 86 PD70741 (a) Read timing (normal access: off-page) (2/2) T1 CLKOUT (output) 96 T2 T2 T2 96 96 97 A0-A23, UBE (output) 99 COL. ROW 98 COL. RAS (output) 100 101 UCAS, LCAS (output) WE (output) 102 103 MRD (output) 104 105 D0-D15 (input/output) (ADC = 0) 104 105 D0-D15 (input/output) (ADC = 1) Remark Broken lines indicate high impedance. 87 PD70741 (b) Write timing (normal access: off-page) (1/2) Parameter Address output delay (relative to CLKOUT) Address output hold time (relative to CLKOUT) RAS output delay (relative to CLKOUT) RAS output hold time (relative to CLKOUT) CAS output delay (relative to CLKOUT) CAS output hold time (relative to CLKOUT) WE output delay (relative to CLKOUT) WE output hold time (relative to CLKOUT) Data active delay (from float, relative to CLKOUT) Data inactive hold time (to float, relative to CLKOUT) 96 97 Symbol tDKA tHKA tDKRAS tHKRAS tDKCAS tHKCAS tDKWE tHKWE tLZKDT tHZKDT Conditions MIN. 2 2 1 1 1 1 1 1 2 2 MAX. 15 15 12 12 12 12 12 12 15 15 Unit ns ns ns ns ns ns ns ns ns ns 98 99 100 101 106 107 108 109 88 PD70741 (b) Write timing (normal access: off-page) (2/2) T1 CLKOUT (output) 96 T2 T2 T2 96 96 97 A0-A23, UBE (output) 99 COL. ROW 98 COL. RAS (output) 100 101 UCAS, LCAS (output) 106 107 WE (output) MRD (output) 108 109 D0-D15 (input/output) (ADC = 0) 108 109 D0-D15 (input/output) (ADC = 1) Remark Broken lines indicate high impedance. 89 PD70741 (c) READY input timing (normal access) Parameter READY setup time (relative to CLKOUT) READY hold time (relative to CLKOUT) 24 Symbol tSRYK tHKRY Conditions MIN. 6 6 MAX. Unit ns ns 25 T2 CLKOUT (output) T2 T2 UCAS, LCAS (output) (read) UCAS, LCAS (output) (write) 24 25 24 25 READY (input) 90 PD70741 [MEMO] 91 PD70741 (d) Read timing (high-speed page access: on-page) (1/2) Parameter Address output delay (relative to CLKOUT) Address output hold time (relative to CLKOUT) CAS output delay (relative to CLKOUT) CAS output hold time (relative to CLKOUT) MRD output delay (relative to CLKOUT) MRD output hold time (relative to CLKOUT) Data input setup time (relative to CLKOUT) Data input hold time (relative to CLKOUT) 96 Symbol tDKA tHKA tDKCAS tHKCAS tDKRD tHKRD tSDK tHKD Conditions MIN. 2 2 1 1 2 2 6 6 MAX. 15 15 12 12 15 15 Unit ns ns ns ns ns ns ns ns 97 100 101 102 103 104 105 92 PD70741 (d) Read timing (high-speed page access: on-page) (2/2) T1 CLKOUT (output) T2 96 97 A0-A23, UBE (output) COL. RAS (output) 100 101 UCAS, LCAS (output) WE (output) 102 103 MRD (output) 104 105 D0-D15 (input/output) (ADC = 0) 104 105 D0-D15 (input/output) (ADC = 1) Remark Broken lines indicate high impedance. 93 PD70741 (e) Write timing (high-speed page access: on-page) (1/2) Parameter Address output delay (relative to CLKOUT) Address output hold time (relative to CLKOUT) CAS output delay (relative to CLKOUT) CAS output hold time (relative to CLKOUT) WE output delay (relative to CLKOUT) WE output hold time (relative to CLKOUT) Data active delay (from float, relative to CLKOUT) Data inactive hold time (to float, relative to CLKOUT) 96 Symbol tDKA tHKA tDKCAS tHKCAS tDKWE tHKWE tLZKDT tHZKDT Conditions MIN. 2 2 1 1 1 1 2 2 MAX. 15 15 12 12 12 12 15 15 Unit ns ns ns ns ns ns ns ns 97 100 101 106 107 108 109 94 PD70741 (e) Write timing (high-speed page access: on-page) (2/2) Note 1 T1 CLKOUT (output) 96 96 97 Note 2 T2 T1 T2 T2 97 A0-A23, UBE (output) COL. COL. RAS (output) 100 101 100 101 UCAS, LCAS (output) 106 107 106 107 WE (output) MRD (output) 108 108 109 109 D0-D15 (input/output) Notes 1. When ADC = 1 and other than DRAM access was performed in the previous cycle 2. Other than the above Remark Broken lines indicate high impedance. 95 PD70741 (7) DRAM, CBR refresh timing Parameter READY setup time (relative to CLKOUT) READY hold time (relative to CLKOUT) RAS pulse width CAS setup time CAS hold time Refresh pulse width RAS precharge to CAS hold time REFRQ active delay (relative to CLKOUT) REFRQ inactive delay (relative to CLKOUT) 24 Symbol tSRYK tHKRY tRAS tCSR tCHR tREF tRPC tDKREF tHKREF Conditions MIN. 6 6 (w + 2.5)T - 20 1T - 20 (w + 2.5)T - 20 (w + 2.5)T - 20 4.5T - 20 1 1 MAX. Unit ns ns ns ns ns ns ns 25 65 110 111 112 113 114 115 12 12 ns ns Remark T: tCYK w: Wait state count for CBR refresh TI CLKOUT (output) TH TH TH TH TH TH TH TH 114 110 112 115 REFRQ (output) 65 RAS (output) 110 111 113 UCAS, LCAS (output) 24 25 24 25 READY (input) Remark In the above timing chart, w = 1 is assumed. 96 PD70741 (8) DRAM, CBR self-refresh timing Parameter CAS setup time REFRQ active delay (relative to CLKOUT) REFRQ inactive delay (relative to CLKOUT) CAS hold time RAS precharge time Symbol 110 114 Conditions MIN. 1T - 20 1 1 -10 4.5T - 20 MAX. Unit ns tCSR tDKREF tHKREF tCHS tRPS 12 12 ns ns ns ns 115 116 117 Remark T: tCYK TI CLKOUT (output) TH TH TH TH TH TH TI 114 115 REFRQ (output) 110 116 117 RAS (output) 110 116 UCAS, LCAS (output) 97 PD70741 (9) Page-ROM access timing (1/2) Parameter Hold time from address to data input Hold time from CSn to data input Hold time from RD to data input Off-page address access time On-page address access time Off-page CSn access time Off-page RD access time 30 Symbol tADH tCDH tRDH tOFPA tONPA tOFCS tOFRD Conditions MIN. 0 0 0 MAX. Unit ns ns ns 32 36 118 (nOFF + 2)T - 25 (nON + 2)T - 25 (nOFF + 2)T - 25 (nOFF + 1.5)T - 25 ns ns ns ns 119 120 121 Remark T nON : tCYK : Wait state count for on-page access (nON = 0, 1) nOFF : Wait state count for off-page access (nOFF = 0-7) 98 PD70741 (9) Page-ROM access timing (2/2) Off-page access T1 CLKOUT (output) T2 T2 T2 On-page access T1 T2 A3-A23Note 1 (output) 118 A0-A2Note 2 (output) 120 119 30 CS3 (output) 32 121 MRD (output) 30 36 D0-D15 (input/output) Notes 1. The address pins to be used vary with the settings of bits MA5 to MA3 of the page-ROM configuration register (PRC). MA5 0 0 0 1 MA4 0 0 1 1 MA3 0 1 1 1 Address A3-A23 A4-A23 A5-A23 A6-A23 2. The address pins to be used vary with the settings of bits MA5 to MA3 of the page-ROM configuration register (PRC). MA5 0 0 0 1 MA4 0 0 1 1 MA3 0 1 1 1 Address A0-A2 A0-A3 A0-A4 A0-A5 Remark Broken lines indicate high impedance. 99 PD70741 (10) Bus hold timing (1/2) Parameter HLDRQ setup time (relative to CLKOUT) HLDRQ hold time (relative to CLKOUT) HLDAK output delay (relative to CLKOUT) HLDAK output hold time (relative to CLKOUT) Delay from address float to HLDAK Delay from HLDAK to address output Delay from data float to HLDAK Delay from HLDAK to data output Symbol 122 Conditions MIN. 6 6 2 2 0.5T - 10 0.5T - 10 1.5T - 15 2T - 15 MAX. Unit ns ns tSHQK tHKHQ tDKHA tHKHA tDAHA tDHAA tDDHA tDHAD 123 124 125 15 15 ns ns ns ns ns ns 126 127 128 129 Remark T: tCYK 100 PD70741 (10) Bus hold timing (2/2) T1 CLKOUT (output) 122 T2 TI TH TH TH TH TI T1 123 122 HLDRQ (input) 124 125 HLDAK (output) 126 127 Note 1 A0-A23 (output) Note 2 MRD (output) CS3 (output) RAS (output) 128 129 D0-D15 (input/output) Notes 1. The level existing immediately before the high-impedance state is held internally. 2. CS2-CS0 (output), UCAS (output), LCAS (output), LMWR/WE (output), UMWR (output), IORD (output), IOWR (output) Remark Broken lines indicate high impedance. 101 PD70741 (11) DMAC timing (1/2) Parameter DREQn setup time (relative to CLKOUT) DREQn hold time (relative to CLKOUT) DACKn output delay (relative to CLKOUT) DACKn output hold time (relative to CLKOUT) TC output delay (relative to CLKOUT) TC output hold time (relative to CLKOUT) Delay from WR to RD Delay from DACK to RD Delay from DACK to WR Delay from RD to DACK Delay from WR to DACK Delay from CAS to IOWR (DRAM read) Delay from IOWR to CAS (DRAM read) Delay from IORD to CAS (DRAM write) Symbol 130 Conditions MIN. 6 6 2 2 2 2 0.5T - 10 0.5T - 10 0.5T - 10 -4 0.5T - 10 (n + 1)T - 10 0.5T - 10 (n + 0.5)T - 10 MAX. Unit ns ns tSDQK tHKDQ tDKDAK tHKDAK tDKTC tHKTC tDWRD tDAKRD tDAKWR tRDDAK tWRDAK tCASWR tWRCAS tRDCAS 131 132 133 15 15 15 15 ns ns ns ns ns ns ns ns ns ns ns ns 134 135 136 137 138 139 140 141 142 143 Remark T: tCYK n: DMA wait state count 102 PD70741 (11) DMAC timing (2/2) T1 CLKOUT (output) 130 131 T2 T1 T2 T2 T3 TI DREQ0, DREQ1 (input) 132 133 DACK0, DACK1 (output) 140 A0-A23, UBE (output) 137 139 MRD, IORD (output) 138 136 136 LMWR/WE, UMWR, IOWR (output) 141 142 141 142 LCAS, UCAS (output) (read) 143 143 LCAS, UCAS (output) (write) 134 135 TC (output) 103 PD70741 (12) INTPn input setup time, hold time Parameter INTPn input low setup time INTPn input high setup time INTPn input low pulse width INTPn input high-level width Symbol 144 Conditions MIN. 9 9 2 2 MAX. Unit ns ns tCYK tCYK tSILK tSIHK tCYIL tCYIH 145 146 147 CLKOUT (output) 145 147 144 146 INTPn (input) (edge mode) 144 INTPn (input) (level mode) (13) NMI input The NMI pin incorporates a noise eliminator which is based on an analog delay (60 to 300 ns). The input setup time and input hold time are not, therefore, specified for NMI. The NMI pin accepts a level input, such that the input level must be held until the acceptance of the input is confirmed after a branch to the handler. NMI (input) Analog delay Internal NMI signal Analog delay Analog delay After confirming acceptance, de-activate NMI from the interrupt handler. CPU processing Normal processing Nonmaskable interrupt handling 104 PD70741 (14) RPU block timing Parameter Timer clock cycle time Timer clock high-level width Timer clock low-level width Timer clear cycle time Timer clear high-level width Timer clear low-level width Timer output high-level width Timer output low-level width Symbol 148 Conditions MIN. 4 2 2 4 2 2 2T - 7 2T - 7 MAX. Unit tCYK tCYK tCYK tCYK tCYK tCYK ns ns tTCYK tTKH tTKL tTCLRY tTCLRH tTCLRL tWTOH tWTOL 149 150 151 152 153 154 155 Remark T: tCYK 148 149 150 TI (input) 151 152 153 TCLR (input) 154 155 TO0n (input) 105 PD70741 (15) CSI timing (a) Master mode Parameter Serial clock cycle time Serial clock high-level width Serial clock low-level width SI setup time (relative to SCLK) SI hold time (relative to SCLK) SO output delay (relative to SCLK) Symbol 156 157 158 Conditions MIN. 4 30 30 20 20 MAX. Unit tCYK ns ns ns ns tCYSK tSKH tSKL tSSISK tHSKSI tDSKSO 159 160 161 30 ns (b) Slave mode Parameter Serial clock cycle time Serial clock high-level width Serial clock low-level width SI setup time (relative to SCLK) SI hold time (relative to SCLK) SO output delay (relative to SCLK) Symbol 156 157 158 Conditions MIN. 4 30 30 20 20 MAX. Unit tCYK ns ns ns ns tCYSK tSKH tSKL tSSISK tHSKSI tDSKSO 159 160 161 30 ns 156 158 157 SCLK (input/output) 161 SO (output) 159 160 SI (input) Remark Broken lines indicate high impedance. 106 PD70741 17. PACKAGE DRAWINGS 100 PIN PLASTIC LQFP (FINE PITCH) (14x14) A B 75 76 51 50 detail of lead end CD S Q R 100 1 26 25 F G P H I M J K M N NOTE Each lead centerline is located within 0.08 mm (0.003 inch) of its true position (T.P.) at maximum material condition. L ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 16.000.20 14.000.20 14.000.20 16.000.20 1.00 1.00 0.22 +0.05 -0.04 0.08 0.50 (T.P.) 1.000.20 0.500.20 0.17 +0.03 -0.07 0.08 1.400.05 0.100.05 3 +7 -3 1.60 MAX. INCHES 0.6300.008 0.551 +0.009 -0.008 0.551 +0.009 -0.008 0.6300.008 0.039 0.039 0.0090.002 0.003 0.020 (T.P.) 0.039 +0.009 -0.008 0.020 +0.008 -0.009 0.007 +0.001 -0.003 0.003 0.0550.002 0.0040.002 3 +7 -3 0.063 MAX. S100GC-50-8EU 107 PD70741 18. RECOMMENDED SOLDERING CONDITIONS The PD70741 should be soldered and mounted under the conditions recommended in the table below. For details of recommended soldering conditions, refer to the information document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact an NEC sales representative. Table 18-1. Surface Mounting Type Soldering Conditions PD70741GC-25-8EU: 100-pin plastic LQFP (fine pitch) (14 x 14 x 1.40 mm) Soldering method Soldering conditions Package peak temperature: 235 C, Duration: 30 sec. Max. (at 210 C or above), Number of times: Twice Max., Time limit: 7 daysNote (thereafter 10 hours prebaking required at 125 C) Infrared reflow VPS VP15-107-2 Partial heating - Note For the storage period after dry-pack decapsulation, storage conditions are Max. 25 C, 65 % RH. Caution Use of more than one soldering method should be avoided (except for partial heating). 108 PD70741 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 109 PD70741 Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: * * * * * Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) Network requirements * In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 NEC Electronics (Germany) GmbH Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 NEC Electronics Hong Kong Ltd. Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics (France) S.A. NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860 NEC Electronics Singapore Pte. Ltd. United Square, Singapore 1130 Tel: 65-253-8311 Fax: 65-250-3583 NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.1. Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 NEC Electronics (Germany) GmbH Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951 NEC do Brasil S.A. Cumbica-Guarulhos-SP, Brasil Tel: 011-6465-6810 Fax: 011-6465-6829 J98. 2 110 PD70741 [MEMO] 111 PD70741 The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. V810, V821, and V810 Family are trademarks of NEC Corporation. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M4 96. 5 |
Price & Availability of UPD70741GC-25-8EU
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |